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AgeCommit message (Expand)Author
2022-10-20target/arm: Split out get_phys_addr_twostageRichard Henderson
2022-10-20target/arm: Use softmmu tlbs for page table walkingRichard Henderson
2022-10-20target/arm: Move be test for regime into S1TranslateResultRichard Henderson
2022-10-20target/arm: Plumb debug into S1TranslateRichard Henderson
2022-10-20target/arm: Split out S1Translate typeRichard Henderson
2022-10-20target/arm: Restrict tlb flush from vttbr_write to vmid changeRichard Henderson
2022-10-20target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idxRichard Henderson
2022-10-20target/arm: Add ARMMMUIdx_Phys_{S,NS}Richard Henderson
2022-10-20target/arm: Use probe_access_full for BTIRichard Henderson
2022-10-20target/arm: Use probe_access_full for MTERichard Henderson
2022-10-20target/arm: Enable TARGET_PAGE_ENTRY_EXTRARichard Henderson
2022-10-20target/arm: update the cortex-a15 MIDR to latest revAlex Bennée
2022-10-18Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
2022-10-18Merge tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi
2022-10-18target/i386: remove old SSE decoderPaolo Bonzini
2022-10-18target/i386: move 3DNow to the new decoderPaolo Bonzini
2022-10-18target/i386: Enable AVX cpuid bits when using TCGPaul Brook
2022-10-18target/i386: implement VLDMXCSR/VSTMXCSRPaolo Bonzini
2022-10-18target/i386: implement XSAVE and XRSTOR of AVX registersPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x28-0x2f, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x10-0x17, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x38, add AVXPaolo Bonzini
2022-10-18target/i386: Use tcg gvec ops for pmovmskbRichard Henderson
2022-10-18target/i386: reimplement 0x0f 0x3a, add AVXPaolo Bonzini
2022-10-18target/i386: clarify (un)signedness of immediates from 0F3Ah opcodesPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x70-0x77, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x78-0x7f, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x50-0x5f, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVXPaolo Bonzini
2022-10-18target/i386: reimplement 0x0f 0x60-0x6f, add AVXPaolo Bonzini
2022-10-18target/i386: Introduce 256-bit vector helpersPaolo Bonzini
2022-10-18target/i386: implement additional AVX comparison operatorsPaolo Bonzini
2022-10-18target/i386: provide 3-operand versions of unary scalar helpersPaolo Bonzini
2022-10-18target/i386: support operand merging in binary scalar helpersPaolo Bonzini
2022-10-18target/i386: extend helpers to support VEX.V 3- and 4- operand encodingsPaolo Bonzini
2022-10-18target/i386: Prepare ops_sse_header.h for 256 bit AVXPaul Brook
2022-10-18target/i386: move scalar 0F 38 and 0F 3A instruction to new decoderPaolo Bonzini
2022-10-18target/i386: validate SSE prefixes directly in the decoding tablePaolo Bonzini
2022-10-18target/i386: validate VEX prefixes via the instructions' exception classesPaolo Bonzini
2022-10-18target/i386: add AVX_EN hflagPaul Brook
2022-10-18target/i386: add CPUID feature checks to new decoderPaolo Bonzini
2022-10-18target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContextPaolo Bonzini
2022-10-18target/i386: add ALU load/writeback corePaolo Bonzini
2022-10-18target/i386: add core of new i386 decoderPaolo Bonzini
2022-10-18target/i386: make rex_w available even in 32-bit modePaolo Bonzini
2022-10-18target/i386: make ldo/sto operations consistent with ldqPaolo Bonzini
2022-10-18target/i386: Define XMMReg and access macros, align ZMM registersRichard Henderson
2022-10-18target/i386: Use probe_access_full for final stage2 translationRichard Henderson