slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-09-13	target/m68k: Honour -semihosting-config userspace=on	Peter Maydell
2022-09-13	target/arm: Honour -semihosting-config userspace=on	Peter Maydell
2022-09-13	semihosting: Allow optional use of semihosting from userspace	Peter Maydell
2022-09-13	target/m68k: Convert semihosting errno to gdb remote errno	Richard Henderson
2022-09-13	target/m68k: Use semihosting/syscalls.h	Richard Henderson
2022-09-13	target/nios2: Convert semihosting errno to gdb remote errno	Richard Henderson
2022-09-13	target/nios2: Use semihosting/syscalls.h	Richard Henderson
2022-09-07	target/riscv: Update the privilege field for sscofpmf CSRs	Atish Patra
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra
2022-09-07	target/riscv: Add few cache related PMU events	Atish Patra
2022-09-07	target/riscv: Simplify counter predicate function	Atish Patra
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra
2022-09-07	target/riscv: Add vstimecmp support	Atish Patra
2022-09-07	target/riscv: Add stimecmp support	Atish Patra
2022-09-07	hw/intc: Move mtimer/mtimecmp to aclint	Atish Patra
2022-09-07	target/riscv: Use official extension names for AIA CSRs	Anup Patel
2022-09-07	target/riscv: Add xicondops in ISA entry	Rahul Pathak
2022-09-07	target/riscv: Remove additional priv version check for mcountinhibit	Atish Patra
2022-09-07	target/riscv: Fix priority of csr related check in riscv_csrrw_check	Weiwei Li
2022-09-07	target/riscv: Add Zihintpause support	Dao Lu
2022-09-07	target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...	eopXD
2022-09-07	target/riscv: rvv: Add mask agnostic for vector permutation instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector mask instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector floating-point instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer comparison instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer shift instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vx instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector load / store instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vv instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V	Alexey Baturo
2022-09-07	target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...	Weiwei Li
2022-09-07	target/riscv: Fix checks in hmode/hmode32	Weiwei Li
2022-09-07	target/riscv: Add check for csrs existed with U extension	Weiwei Li
2022-09-07	target/riscv: Fix checkpatch warning may triggered in csr_ops table	Weiwei Li
2022-09-07	target/riscv: H extension depends on I extension	Weiwei Li
2022-09-07	target/riscv: Add check for supported privilege mode combinations	Weiwei Li
2022-09-07	target/riscv: move zmmul out of the experimental properties	Weiwei Li
2022-09-07	target/riscv: fix shifts shamt value for rv128c	Frédéric Pétrot
2022-09-07	target/riscv: Force disable extensions if priv spec version does not match	Anup Patel
2022-09-07	target/riscv: Update [m\|h]tinst CSR in riscv_cpu_do_interrupt()	Anup Patel
2022-09-06	target/riscv: Make translator stop before the end of a page	Richard Henderson
2022-09-06	target/riscv: Add MAX_INSN_LEN and insn_len	Richard Henderson
2022-09-06	target/i386: Make translator stop before the end of a page	Ilya Leoshkevich
2022-09-06	target/s390x: Make translator stop before the end of a page	Ilya Leoshkevich
2022-09-06	accel/tcg: Add pc and host_pc params to gen_intermediate_code	Richard Henderson
2022-09-06	accel/tcg: Remove translator_ldsw	Richard Henderson
2022-09-04	target/openrisc: Interrupt handling fixes	Stafford Horne
2022-09-04	target/openrisc: Enable MTTCG	Stafford Horne
2022-09-04	target/openrisc: Add interrupted CPU to log	Stafford Horne