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2022-05-05target/ppc: Remove msr_pr macroVíctor Colombo
msr_pr macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: Remove unused msr_* macrosVíctor Colombo
Some msr_* macros are not used anywhere. Remove them as part of the work to remove all hidden usage of *env. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220504210541.115256-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: Remove fpscr_* macros from cpu.hVíctor Colombo
fpscr_* defined macros are hiding the usage of *env behind them. Substitute the usage of these macros with `env->fpscr & FP_*` to make the code cleaner. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220504210541.115256-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: Fix BookE debug interrupt generationBin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug Event" and chapter 8.4.5 "Instruction Complete Debug Event": "A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT] are set ... Branch taken debug events are not recognized if MSR[DE] is cleared when the branch instruction executes." "An instruction complete debug event occurs when any instruction completes execution so long as MSR[DE] and DBCR0[ICMP] are both set ... Instruction complete debug events are not recognized if MSR[DE] is cleared at the time of the instruction execution." Current codes do not check MSR.DE bit before setting HFLAGS_SE and HFLAGS_BE flag, which would cause the immediate debug interrupt to be generated, e.g.: when DBCR0.ICMP bit is set by guest software and MSR.DE is not set. [1] https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220421011729.1148727-1-bmeng.cn@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: init 'rmmu_info' in kvm_get_radix_page_info()Daniel Henrique Barboza
Init the struct to avoid Valgrind complaints about unitialized bytes, such as this one: ==39549== Syscall param ioctl(generic) points to uninitialised byte(s) ==39549== at 0x55864E4: ioctl (in /usr/lib64/libc.so.6) ==39549== by 0xD1F7EF: kvm_vm_ioctl (kvm-all.c:3035) ==39549== by 0xAF8F5B: kvm_get_radix_page_info (kvm.c:276) ==39549== by 0xB00533: kvmppc_host_cpu_class_init (kvm.c:2369) ==39549== by 0xD3DCE7: type_initialize (object.c:366) ==39549== by 0xD3FACF: object_class_foreach_tramp (object.c:1071) ==39549== by 0x502757B: g_hash_table_foreach (in /usr/lib64/libglib-2.0.so.0.7000.5) ==39549== by 0xD3FC1B: object_class_foreach (object.c:1093) ==39549== by 0xB0141F: kvm_ppc_register_host_cpu_type (kvm.c:2613) ==39549== by 0xAF87E7: kvm_arch_init (kvm.c:157) ==39549== by 0xD1E2A7: kvm_init (kvm-all.c:2595) ==39549== by 0x8E6E93: accel_init_machine (accel-softmmu.c:39) ==39549== Address 0x1fff00e208 is on thread 1's stack ==39549== in frame #2, created by kvm_get_radix_page_info (kvm.c:267) ==39549== Uninitialised value was created by a stack allocation ==39549== at 0xAF8EE8: kvm_get_radix_page_info (kvm.c:267) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220331001717.616938-5-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: init 'sregs' in kvmppc_put_books_sregs()Daniel Henrique Barboza
Init 'sregs' to avoid Valgrind complaints about uninitialized bytes from kvmppc_put_books_sregs(): ==54059== Thread 3: ==54059== Syscall param ioctl(generic) points to uninitialised byte(s) ==54059== at 0x55864E4: ioctl (in /usr/lib64/libc.so.6) ==54059== by 0xD1FA23: kvm_vcpu_ioctl (kvm-all.c:3053) ==54059== by 0xAFB18B: kvmppc_put_books_sregs (kvm.c:891) ==54059== by 0xAFB47B: kvm_arch_put_registers (kvm.c:949) ==54059== by 0xD1EDA7: do_kvm_cpu_synchronize_post_init (kvm-all.c:2766) ==54059== by 0x481AF3: process_queued_cpu_work (cpus-common.c:343) ==54059== by 0x4EF247: qemu_wait_io_event_common (cpus.c:412) ==54059== by 0x4EF343: qemu_wait_io_event (cpus.c:436) ==54059== by 0xD21E83: kvm_vcpu_thread_fn (kvm-accel-ops.c:54) ==54059== by 0xFFEBF3: qemu_thread_start (qemu-thread-posix.c:556) ==54059== by 0x54E6DC3: start_thread (in /usr/lib64/libc.so.6) ==54059== by 0x5596C9F: clone (in /usr/lib64/libc.so.6) ==54059== Address 0x799d1cc is on thread 3's stack ==54059== in frame #2, created by kvmppc_put_books_sregs (kvm.c:851) ==54059== Uninitialised value was created by a stack allocation ==54059== at 0xAFAEB0: kvmppc_put_books_sregs (kvm.c:851) This happens because Valgrind does not consider the 'sregs' initialization done by kvm_vcpu_ioctl() at the end of the function. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220331001717.616938-4-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: init 'lpcr' in kvmppc_enable_cap_large_decr()Daniel Henrique Barboza
'lpcr' is used as an input of kvm_get_one_reg(). Valgrind doesn't understand that and it returns warnings as such for this function: ==55240== Thread 1: ==55240== Conditional jump or move depends on uninitialised value(s) ==55240== at 0xB011E4: kvmppc_enable_cap_large_decr (kvm.c:2546) ==55240== by 0x92F28F: cap_large_decr_cpu_apply (spapr_caps.c:523) ==55240== by 0x930C37: spapr_caps_cpu_apply (spapr_caps.c:921) ==55240== by 0x955D3B: spapr_reset_vcpu (spapr_cpu_core.c:73) ==55240== by 0x95612B: spapr_cpu_core_reset (spapr_cpu_core.c:209) ==55240== by 0x95619B: spapr_cpu_core_reset_handler (spapr_cpu_core.c:218) ==55240== by 0xD3605F: qemu_devices_reset (reset.c:69) ==55240== by 0x92112B: spapr_machine_reset (spapr.c:1641) ==55240== by 0x4FBD63: qemu_system_reset (runstate.c:444) ==55240== by 0x62812B: qdev_machine_creation_done (machine.c:1247) ==55240== by 0x5064C3: qemu_machine_creation_done (vl.c:2725) ==55240== by 0x5065DF: qmp_x_exit_preconfig (vl.c:2748) ==55240== Uninitialised value was created by a stack allocation ==55240== at 0xB01158: kvmppc_enable_cap_large_decr (kvm.c:2540) Init 'lpcr' to avoid this warning. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220331001717.616938-3-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/ppc: initialize 'val' union in kvm_get_one_spr()Daniel Henrique Barboza
Valgrind isn't convinced that we are initializing the values we assign to env->spr[spr] because it doesn't understand that the 'val' union is being written by the kvm_vcpu_ioctl() that follows (via struct kvm_one_reg). This results in Valgrind complaining about uninitialized values every time we use env->spr in a conditional, like this instance: ==707578== Thread 1: ==707578== Conditional jump or move depends on uninitialised value(s) ==707578== at 0xA10A40: hreg_compute_hflags_value (helper_regs.c:106) ==707578== by 0xA10C9F: hreg_compute_hflags (helper_regs.c:173) ==707578== by 0xA110F7: hreg_store_msr (helper_regs.c:262) ==707578== by 0xA051A3: ppc_cpu_reset (cpu_init.c:7168) ==707578== by 0xD4730F: device_transitional_reset (qdev.c:799) ==707578== by 0xD4A11B: resettable_phase_hold (resettable.c:182) ==707578== by 0xD49A77: resettable_assert_reset (resettable.c:60) ==707578== by 0xD4994B: resettable_reset (resettable.c:45) ==707578== by 0xD458BB: device_cold_reset (qdev.c:296) ==707578== by 0x48FBC7: cpu_reset (cpu-common.c:114) ==707578== by 0x97B5EB: spapr_reset_vcpu (spapr_cpu_core.c:38) ==707578== by 0x97BABB: spapr_cpu_core_reset (spapr_cpu_core.c:209) ==707578== Uninitialised value was created by a stack allocation ==707578== at 0xB11F08: kvm_get_one_spr (kvm.c:543) Initializing 'val' has no impact in the logic and makes Valgrind output more bearable. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220331001717.616938-2-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05target/arm: read access to performance counters from EL0Alex Zuepke
The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. Signed-off-by: Alex Zuepke <alex.zuepke@tum.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220428132717.84190-1-alex.zuepke@tum.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Add isar_feature_{aa64,any}_rasRichard Henderson
Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Add isar predicates for FEAT_Debugv8p2Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtableRichard Henderson
Since e03b56863d2bc, our host endian indicator is unconditionally set, which means that we can use a normal C condition. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-20-richard.henderson@linaro.org [PMM: quote correct git hash in commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Reformat comments in add_cpreg_to_hashtableRichard Henderson
Put the block comments into the current coding style. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Perform override check early in add_cpreg_to_hashtableRichard Henderson
Perform the override check early, so that it is still done even when we decide to discard an unreachable cpreg. Use assert not printf+abort. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Hoist isbanked computation in add_cpreg_to_hashtableRichard Henderson
Computing isbanked only once makes the code a bit easier to read. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Use bool for is64 and ns in add_cpreg_to_hashtableRichard Henderson
Bool is a more appropriate type for these variables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Consolidate cpreg updates in add_cpreg_to_hashtableRichard Henderson
Put most of the value writeback to the same place, and improve the comment that goes with them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Hoist computation of key in add_cpreg_to_hashtableRichard Henderson
Move the computation of key to the top of the function. Hoist the resolution of cp as well, as an input to the computation of key. This will be required by a subsequent patch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Merge allocation of the cpreg and its nameRichard Henderson
Simplify freeing cp_regs hash table entries by using a single allocation for the entire value. This fixes a theoretical bug if we were to ever free the entire hash table, because we've been installing string literal constants into the cpreg structure in define_arm_vh_e2h_redirects_aliases. However, at present we only free entries created for AArch32 wildcard cpregs which get overwritten by more specific cpregs, so this bug is never exposed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Store cpregs key in the hash table directlyRichard Henderson
Cast the uint32_t key into a gpointer directly, which allows us to avoid allocating storage for each key. Use g_hash_table_lookup when we already have a gpointer (e.g. for callbacks like count_cpreg), or when using get_arm_cp_reginfo would require casting away const. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliasesRichard Henderson
The new_key field is always non-zero -- drop the if. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-11-richard.henderson@linaro.org [PMM: reinstated dropped PL3_RW mask] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Name CPSecureState typeRichard Henderson
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Name CPState typeRichard Henderson
Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Change cpreg access permissions to enumRichard Henderson
Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Avoid bare abort() or assert(0)Richard Henderson
Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Reorg ARMCPRegInfo type field bitsRichard Henderson
Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Make some more cpreg data static constRichard Henderson
These particular data structures are not modified at runtime. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson
Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Reorg CPAccessResult and access_check_cp_regRichard Henderson
Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Split out cpregs.hRichard Henderson
Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-userRichard Henderson
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3 (indirect branch from register other than x16/x17). The linux kernel sets this in bti_enable(). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220427042312.294300-1-richard.henderson@linaro.org [PMM: remove stray change to makefile comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-04disas: Remove old libopcode s390 disassemblerThomas Huth
Capstone should be superior to the old libopcode disassembler, so we can drop the old file nowadays. Message-Id: <20220412165836.355850-2-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU modelDavid Miller
[ dh: take care of compat machines ] Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-13-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: vector {load, store} byte reversed elementDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-12-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: vector {load, store} byte reversed elementsDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-11-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: vector {load, store} elements reversedDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-10-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: vector shift double by bitDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220428094708.84835-9-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: Update for changes to vector shiftsDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: vector string searchDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-7-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: vxeh2: vector convert short/32bDavid Miller
Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-6-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04s390x/cpu_models: make "max" match the unmodified "qemu" CPU model under TCGDavid Hildenbrand
Before we were able to bump up the qemu CPU model to a z13, we included some experimental features during development in the "max" model only. Nowadays, the "max" model corresponds exactly to the "qemu" CPU model of the latest QEMU machine under TCG. Let's remove all the special casing, effectively making both models match completely from now on, and clean up. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220428094708.84835-4-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04s390x/cpu_models: drop "msa5" from the TCG "max" modelDavid Hildenbrand
We don't include the "msa5" feature in the "qemu" model because it generates a warning. The PoP states: "The message-security-assist extension 5 requires the secure-hash-algorithm (SHA-512) capabilities of the message-security-assist extension 2 as a prereq- uisite. (March, 2015)" As SHA-512 won't be supported in the near future, let's just drop the feature from the "max" model. This avoids the warning and allows us for making the "max" model match the "qemu" model (except for compat machines). We don't lose much, as we only implement the function stubs for MSA, excluding any real subfunctions. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/897 Message-Id: <20220428094708.84835-3-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04target/s390x: Fix writeback to v1 in helper_vstlRichard Henderson
Fixes: 0e0a5b49ad58 ("s390x/tcg: Implement VECTOR STORE WITH LENGTH") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Miller <dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-2-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-29target/riscv: add scalar crypto related extenstion strings to isa_stringWeiwei Li
- add zbk* and zk* strings to isa_edata_arr Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: Fix incorrect PTE merge in walk_pteRalf Ramsauer
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this case, walk_pte will erroneously merge them. Enforce the split up, by tracking the virtual base address. Let's say we have the mapping: 0x81200000 -> 0x89623000 (4K) 0x8120f000 -> 0x89624000 (4K) Before, walk_pte would have shown: vaddr paddr size attr ---------------- ---------------- ---------------- ------- 0000000081200000 0000000089623000 0000000000002000 rwxu-ad as it only checks for subsequent paddrs. With this patch, it becomes: vaddr paddr size attr ---------------- ---------------- ---------------- ------- 0000000081200000 0000000089623000 0000000000001000 rwxu-ad 000000008120f000 0000000089624000 0000000000001000 rwxu-ad Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: expose zbk* and zk* propertiesWeiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li
- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in ↵Weiwei Li
zknh extension - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in ↵Weiwei Li
zknh extension - add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-19 08:41:47 +0000