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AgeCommit message (Expand)Author
2021-05-04target/ppc: Validate hflags with CONFIG_DEBUG_TCGRichard Henderson
2021-05-04target/ppc: Remove env->immu_idx and env->dmmu_idxRichard Henderson
2021-05-04target/ppc: Remove MSR_SA and MSR_AP from hflagsRichard Henderson
2021-05-04target/ppc: Put LPCR[GTSE] in hflagsRichard Henderson
2021-05-04target/ppc: Create helper_scvRichard Henderson
2021-05-04target/ppc: Put dbcr0 single-step bits into hflagsRichard Henderson
2021-05-04target/ppc: Reduce env->hflags to uint32_tRichard Henderson
2021-05-04target/ppc: Disconnect hflags from MSRRichard Henderson
2021-05-04target/ppc: Extract post_load_update_msrRichard Henderson
2021-05-04target/ppc: Fix comment for MSR_FE{0,1}Richard Henderson
2021-05-04target/ppc: Retain hflags_nmsr only for migrationRichard Henderson
2021-05-04target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msrRichard Henderson
2021-05-04target/ppc: Properly sync cpu state with new msr in cpu_load_oldRichard Henderson
2021-05-04target/ppc: Move 601 hflags adjustment to hreg_compute_hflagsRichard Henderson
2021-05-04target/ppc: Move helper_regs.h functions out-of-lineRichard Henderson
2021-05-01Hexagon (target/hexagon) CABAC decode binTaylor Simpson
2021-05-01Hexagon (target/hexagon) load into shifted register instructionsTaylor Simpson
2021-05-01Hexagon (target/hexagon) load and unpack bytes instructionsTaylor Simpson
2021-05-01Hexagon (target/hexagon) bit reverse (brev) addressingTaylor Simpson
2021-05-01Hexagon (target/hexagon) circular addressingTaylor Simpson
2021-05-01Hexagon (target/hexagon) add A4_addp_c/A4_subp_cTaylor Simpson
2021-05-01Hexagon (target/hexagon) add A6_vminub_RdPTaylor Simpson
2021-05-01Hexagon (target/hexagon) add A5_ACS (vacsh)Taylor Simpson
2021-05-01Hexagon (target/hexagon) add F2_sfinvsqrtaTaylor Simpson
2021-05-01Hexagon (target/hexagon) add F2_sfrecipa instructionTaylor Simpson
2021-05-01Hexagon (target/hexagon) compile all debug codeTaylor Simpson
2021-05-01Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.hTaylor Simpson
2021-05-01Hexagon (target/hexagon) cleanup reg_field_info definitionTaylor Simpson
2021-05-01Hexagon (target/hexagon) cleanup ternary operators in semanticsTaylor Simpson
2021-05-01Hexagon (target/hexagon) use softfloat for float-to-int conversionsTaylor Simpson
2021-05-01Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbnTaylor Simpson
2021-05-01Hexagon (target/hexagon) use softfloat default NaN and tininessTaylor Simpson
2021-05-01Hexagon (target/hexagon) change type of softfloat_roundingmodesTaylor Simpson
2021-05-01Hexagon (target/hexagon) remove unused carry_from_add64 functionTaylor Simpson
2021-05-01Hexagon (target/hexagon) change variables from int to bool when appropriateTaylor Simpson
2021-05-01Hexagon (target/hexagon) decide if pred has been written at TCG gen timeTaylor Simpson
2021-05-01Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURNTaylor Simpson
2021-05-01Hexagon (target/hexagon) use env_archcpu and env_cpuTaylor Simpson
2021-05-01Hexagon (target/hexagon) remove unnecessary inline directivesTaylor Simpson
2021-05-01Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pairTaylor Simpson
2021-05-01Hexagon (target/hexagon) TCG generation cleanupTaylor Simpson
2021-05-01target/hexagon: remove unnecessary semicolonsTaylor Simpson
2021-05-01target/hexagon: fix typo in commentTaylor Simpson
2021-05-01target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUMTaylor Simpson
2021-05-01target/hexagon: remove unnecessary checks in find_iclass_slotsTaylor Simpson
2021-05-01target/hexagon: translation changesTaylor Simpson
2021-04-30target/arm: Enforce alignment for sve LD1RRichard Henderson
2021-04-30target/arm: Enforce alignment for aa64 vector LDn/STn (single)Richard Henderson
2021-04-30target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)Richard Henderson
2021-04-30target/arm: Use MemOp for size + endian in aa64 vector ld/stRichard Henderson