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2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
Introduction of a gen_logic function for bitwise logic to implement instructions in which no propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-6-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot
Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation. Although RV128 is a superset of RV64, we keep for now the RV64 only tests for extensions other than RVI and RVM. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-5-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set them to be enabled by default, the comment about experimental extensions was kept in place above them. This moves it down a few lines to only cover experimental extensions. References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106134020.1628889-1-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ↵Frank Chang
fp/int type-convert insns vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width floating-point. Therefore, should use require_rvf() to check whether RVF/RVD is enabled. vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to single-width integer. Therefore, should use require_scale_rvf() to check whether RVF/RVD is enabled. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220105022247.21131-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening ↵Frank Chang
fp/int type-convert insns vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v convert single-width floating-point to double-width integer. Therefore, should use require_rvf() to check whether RVF/RVD is enabled. vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width floating-point, and vfwcvt.f.f.v convert double-width floating-point to single-width floating-point. Therefore, should use require_scale_rvf() to check whether RVF/RVD is enabled. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220105022247.21131-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening ↵Frank Chang
fp insns Vector widening floating-point instructions should use require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is enabled. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220105022247.21131-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis
Let's enable the Hypervisor extension by default. This doesn't affect named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the Hypervisor extensions by default for the virt machine. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com>
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis
The Hypervisor spec is now frozen, so remove the experimental tag. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220105213937.1113508-6-alistair.francis@opensource.wdc.com>
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin
As per the privilege specification, any access from S/U mode should fail if no pmp region is configured and pmp is present, othwerwise access should succeed. Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is configured) Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211214092659.15709-1-nikita.shubin@maquefel.me Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07target/arm: Add missing FEAT_TLBIOS instructionsIdan Horowitz
Some of the instructions added by the FEAT_TLBIOS extension were forgotten when the extension was originally added to QEMU. Fixes: 7113d618505b ("target/arm: Add support for FEAT_TLBIOS") Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211231103928.1455657-1-idan.horowitz@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-06linux-user/nios2: Map a real kuser pageRichard Henderson
The first word of page1 is data, so the whole thing can't be implemented with emulation of addresses. Use init_guest_commpage for the allocation. Hijack trap number 16 to implement cmpxchg. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211221025012.1057923-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-06linux-user/nios2: Properly emulate EXCP_TRAPRichard Henderson
The real kernel has to load the instruction and extract the imm5 field; for qemu, modify the translator to do this. The use of R_AT for this in cpu_loop was a bug. Handle the other trap numbers as per the kernel's trap_table. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211221025012.1057923-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-06target/sh4: Implement prctl_unalign_sigbusRichard Henderson
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211227150127.2659293-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-06target/hppa: Implement prctl_unalign_sigbusRichard Henderson
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211227150127.2659293-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-06target/alpha: Implement prctl_unalign_sigbusRichard Henderson
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211227150127.2659293-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-04target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()Daniel Henrique Barboza
MMCR0 writes will change only MMCR0 bits which are used to calculate HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine register will be changed during this operation. This means that hreg_compute_hflags() is overkill for what we need to do. pmu_update_summaries() is already updating HFLAGS_INSN_CNT without calling hreg_compure_hflags(). Let's do the same for the other 2 MMCR0 hflags. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220103224746.167831-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Use env->pnc_cyc_cntRichard Henderson
Use the cached pmc_cyc_cnt value in pmu_update_cycles and pmc_update_overflow_timer. This leaves pmc_get_event and pmc_is_inactive unused, so remove them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103224746.167831-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Rewrite pmu_increment_insnsRichard Henderson
Use the cached pmc_ins_cnt value. Unroll the loop over the different PMC counters. Treat the PMC4 run-latch specially. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103224746.167831-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Cache per-pmc insn and cycle count settingsRichard Henderson
This is the combination of frozen bit and counter type, on a per counter basis. So far this is only used by HFLAGS_INSN_CNT, but will be used more later. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [danielhb: fixed PMC4 cyc_cnt shift, insn run latch code, MMCR0_FC handling, "PMC[1-6]" comment] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220103224746.167831-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Stop passing excp_model aroundFabiano Rosas
We can just access it directly in powerpc_excp. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ clg: Took into account removal of inline ] Message-Id: <20211229165751.3774248-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Move system call vectored code togetherFabiano Rosas
Now that 'vector' is known before calling the interrupt-specific setup code, we can move all of the scv setup into one place. No functional change intended. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211229165751.3774248-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Set vector earlierFabiano Rosas
None of the interrupt setup code touches 'vector', so we can move it earlier in the function. This will allow us to later move the System Call Vectored setup that is on the top level into the POWERPC_EXCP_SYSCALL_VECTORED code block. This patch also moves the verification for when 'excp' does not have an address associated with it. We now bail a little earlier when that is the case. This should not cause any visible effects. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Add excp_vectors bounds checkFabiano Rosas
The next patch will start accessing the excp_vectors array earlier in the function, so add a bounds check as first thing here. This converts the empty return on POWERPC_EXCP_NONE to an error. This exception number never reaches this function and if it does it probably means something else went wrong up the line. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Set alternate SRRs directlyFabiano Rosas
There are currently only two interrupts that use alternate SRRs, so let them write to them directly during the setup code. No functional change intended. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: do not silence snan in xscvspdpnMatheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer precision insns doesn't silence SNaNs in the hardware. To better match this behavior, use the non-arithmatic conversion of helper_todouble instead of float32_to_float64. A test is added to prevent future regressions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211228120310.1957990-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Dump specific registersCédric Le Goater
Rework slightly ppc_cpu_dump_state() to replace the various 'if' statements with a 'switch'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-9-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-10-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Introduce a store helper for SPR_40x_PIDCédric Le Goater
The PID SPR of the 405 CPU contains the translation ID of the TLB which is a 8-bit field. Enforce the mask with a store helper. Cc: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-8-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-9-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Restore TCR and STR write handlersCédric Le Goater
The 405 timers were broken when booke support was added. Assumption was made that the register numbers were the same but it's not : SPR_BOOKE_TSR (0x150) SPR_BOOKE_TCR (0x154) SPR_40x_TSR (0x3D8) SPR_40x_TCR (0x3DA) Cc: Christophe Leroy <christophe.leroy@c-s.fr> Fixes: ddd1055b07fd ("PPC: booke timers") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Activate MMU logsCédric Le Goater
There is no need to deactivate MMU logging at compile time. Remove all use of defines. Only keep DUMP_PAGE_TABLES for another series since page tables could be dumped from the monitor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Print out literal exception names in logsCédric Le Goater
It facilitates reading the logs when mask CPU_LOG_INT is activated. We should do the same for error codes. Cc: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211222064025.1541490-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Remove static inlineCédric Le Goater
The compiler should know better how to inline code if necessary. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Check effective address validityCédric Le Goater
For Radix translation, the EA range is 64-bits. when EA(2:11) are nonzero, a segment interrupt should occur. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20211231073122.3183583-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Improve logging in Radix MMUCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211222071002.1568894-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-30target/hppa: Fix atomic_store_3 for STBYRichard Henderson
The parallel version of STBY did not take host endianness into account, and also computed the incorrect address for STBY_E. Bswap twice to handle the merge and store. Compute mask inside the function rather than as a parameter. Force align the address, rather than subtracting one. Generalize the function to system mode by using probe_access(). Cc: qemu-stable@nongnu.org Tested-by: Helge Deller <deller@gmx.de> Reported-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-23target/hppa: Fix deposit assert from trans_shrpw_immRichard Henderson
Because sa may be 0, tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); may attempt a zero-width deposit at bit 32, which will assert for TARGET_REGISTER_BITS == 32. Use the newer extract2 when possible, which itself includes the rotri special case; otherwise mirror the code from trans_shrpw_sar, using concat and shri. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/635 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta
The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
SEW has the limitation which cannot exceed ELEN. Widening instructions have a destination group with EEW = 2*SEW and narrowing instructions have a source operand with EEW = 2*SEW. Both of the instructions have the limitation of: 2*SEW <= ELEN. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-78-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-77-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and ↵Frank Chang
vmorn.mm Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang
Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-71-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate ↵Frank Chang
instruction Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-70-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-69-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang
If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trigger illegal instruction exception if frm field contains invalid value at run-time for vector floating-point instructions. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-68-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
* Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads) to raise the memory access exception at the exact processed vector element. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 08:37:13 +0000