aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2019-06-03i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitorWanpeng Li
2019-06-01target/mips: Improve performance of certain MSA instructionsMateja Marjanovic
2019-06-01target/mips: Clean up lmi_helper.cAleksandar Markovic
2019-06-01target/mips: Clean up dsp_helper.cAleksandar Markovic
2019-06-01target/mips: Add emulation of MMI instruction PCPYUDMateja Marjanovic
2019-06-01target/mips: Add emulation of MMI instruction PCPYLDMateja Marjanovic
2019-06-01target/mips: Add emulation of MMI instruction PCPYHMateja Marjanovic
2019-05-29spapr/xive: add KVM supportCédric Le Goater
2019-05-29target/ppc: Use vector variable shifts for VSL, VSR, VSRARichard Henderson
2019-05-29target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]pAnton Blanchard
2019-05-29target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STOREAnton Blanchard
2019-05-29target/ppc: Fix xxspltibAnton Blanchard
2019-05-29target/ppc: Fix vsum2swsAnton Blanchard
2019-05-29target/ppc: Fix vslv and vsrvAnton Blanchard
2019-05-29target/ppc: Fix xxbrq, xxbrwAnton Blanchard
2019-05-29target/ppc: Fix xvxsigdpAnton Blanchard
2019-05-29target/ppc/kvm: Fix trace typoBoxuan Li
2019-05-28Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2...Peter Maydell
2019-05-28Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v...Peter Maydell
2019-05-28target/mips: convert UHI_plog to use common semihosting codeAlex Bennée
2019-05-28target/mips: only build mips-semi for softmmuAlex Bennée
2019-05-28target/arm: correct return values for WRITE/READ in arm-semiAlex Bennée
2019-05-28target/arm: add LOG_UNIMP messages to arm-semiAlex Bennée
2019-05-28target/arm: use the common interface for WRITE0/WRITEC in arm-semiAlex Bennée
2019-05-28target/arm: fixup some of the commentary for arm-semiAlex Bennée
2019-05-28semihosting: move semihosting configuration into its own directoryAlex Bennée
2019-05-26target/mips: realign comments to fix checkpatch warningsJules Irenge
2019-05-26target/mips: add or remove space to fix checkpatch errorsJules Irenge
2019-05-26mips: Decide to map PAGE_EXEC in map_addressJakub Jermář
2019-05-26target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic
2019-05-26target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic
2019-05-26target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic
2019-05-26target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic
2019-05-26target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic
2019-05-26target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic
2019-05-26target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens
2019-05-24target/riscv: Add checks for several RVC reserved operandsRichard Henderson
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis
2019-05-24target/riscv: Improve the scause logicAlistair Francis
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis
2019-05-24target/riscv: Remove spaces from register namesRichard Henderson