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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2019-06-03
i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor
Wanpeng Li
2019-06-01
target/mips: Improve performance of certain MSA instructions
Mateja Marjanovic
2019-06-01
target/mips: Clean up lmi_helper.c
Aleksandar Markovic
2019-06-01
target/mips: Clean up dsp_helper.c
Aleksandar Markovic
2019-06-01
target/mips: Add emulation of MMI instruction PCPYUD
Mateja Marjanovic
2019-06-01
target/mips: Add emulation of MMI instruction PCPYLD
Mateja Marjanovic
2019-06-01
target/mips: Add emulation of MMI instruction PCPYH
Mateja Marjanovic
2019-05-29
spapr/xive: add KVM support
Cédric Le Goater
2019-05-29
target/ppc: Use vector variable shifts for VSL, VSR, VSRA
Richard Henderson
2019-05-29
target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p
Anton Blanchard
2019-05-29
target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE
Anton Blanchard
2019-05-29
target/ppc: Fix xxspltib
Anton Blanchard
2019-05-29
target/ppc: Fix vsum2sws
Anton Blanchard
2019-05-29
target/ppc: Fix vslv and vsrv
Anton Blanchard
2019-05-29
target/ppc: Fix xxbrq, xxbrw
Anton Blanchard
2019-05-29
target/ppc: Fix xvxsigdp
Anton Blanchard
2019-05-29
target/ppc/kvm: Fix trace typo
Boxuan Li
2019-05-28
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2...
Peter Maydell
2019-05-28
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v...
Peter Maydell
2019-05-28
target/mips: convert UHI_plog to use common semihosting code
Alex Bennée
2019-05-28
target/mips: only build mips-semi for softmmu
Alex Bennée
2019-05-28
target/arm: correct return values for WRITE/READ in arm-semi
Alex Bennée
2019-05-28
target/arm: add LOG_UNIMP messages to arm-semi
Alex Bennée
2019-05-28
target/arm: use the common interface for WRITE0/WRITEC in arm-semi
Alex Bennée
2019-05-28
target/arm: fixup some of the commentary for arm-semi
Alex Bennée
2019-05-28
semihosting: move semihosting configuration into its own directory
Alex Bennée
2019-05-26
target/mips: realign comments to fix checkpatch warnings
Jules Irenge
2019-05-26
target/mips: add or remove space to fix checkpatch errors
Jules Irenge
2019-05-26
mips: Decide to map PAGE_EXEC in map_address
Jakub Jermář
2019-05-26
target/mips: Refactor and fix INSERT.<B|H|W|D> instructions
Mateja Marjanovic
2019-05-26
target/mips: Refactor and fix COPY_U.<B|H|W> instructions
Mateja Marjanovic
2019-05-26
target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
Mateja Marjanovic
2019-05-26
target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
Mateja Marjanovic
2019-05-26
target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
Mateja Marjanovic
2019-05-26
target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware
Mateja Marjanovic
2019-05-26
target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware
Mateja Marjanovic
2019-05-24
target/riscv: Only flush TLB if SATP.ASID changes
Jonathan Behrens
2019-05-24
target/riscv: More accurate handling of `sip` CSR
Jonathan Behrens
2019-05-24
target/riscv: Add checks for several RVC reserved operands
Richard Henderson
2019-05-24
target/riscv: Add the HGATP register masks
Alistair Francis
2019-05-24
target/riscv: Add the HSTATUS register masks
Alistair Francis
2019-05-24
target/riscv: Add Hypervisor CSR macros
Alistair Francis
2019-05-24
target/riscv: Allow setting mstatus virtulisation bits
Alistair Francis
2019-05-24
target/riscv: Add the MPV and MTL mstatus bits
Alistair Francis
2019-05-24
target/riscv: Improve the scause logic
Alistair Francis
2019-05-24
target/riscv: Trigger interrupt on MIP update asynchronously
Alistair Francis
2019-05-24
target/riscv: Mark privilege level 2 as reserved
Alistair Francis
2019-05-24
target/riscv: Add a base 32 and 64 bit CPU
Alistair Francis
2019-05-24
target/riscv: Create settable CPU properties
Alistair Francis
2019-05-24
target/riscv: Remove spaces from register names
Richard Henderson
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