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2022-02-22Merge remote-tracking branch ↵Peter Maydell
'remotes/lvivier-gitlab/tags/trivial-branch-for-7.0-pull-request' into staging Trivial branch pull request 20220222 # gpg: Signature made Tue 22 Feb 2022 16:16:01 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/lvivier-gitlab/tags/trivial-branch-for-7.0-pull-request: hid: Implement support for side and extra buttons vdpa: Make ncs autofree qemu-options: fix incorrect description for '-drive index=' hw/nvram: use at24 macro target/rx: Remove unused ENV_OFFSET definition target/avr: Correct AVRCPUClass docstring configure: Disable capstone and slirp in the --without-default-features mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-22Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2022-02-21' into staging * Improve virtio-net failover test * Some small fixes for the qtests * Misc header cleanups by Philippe # gpg: Signature made Mon 21 Feb 2022 11:40:37 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2022-02-21: (25 commits) hw/tricore: Remove unused and incorrect header hw/m68k/mcf: Add missing 'exec/hwaddr.h' header exec/exec-all: Move 'qemu/log.h' include in units requiring it softmmu/runstate: Clean headers linux-user: Add missing "qemu/timer.h" include target: Add missing "qemu/timer.h" include core/ptimers: Remove unnecessary 'sysemu/cpus.h' include exec/ramblock: Add missing includes qtest: Add missing 'hw/qdev-core.h' include hw/acpi/memory_hotplug: Remove unused 'hw/acpi/pc-hotplug.h' header hw/remote: Add missing include hw/tpm: Clean includes scripts: Remove the old switch-timer-api script tests/qtest: failover: migration abort test with failover off tests/qtest: failover: test migration if the guest doesn't support failover tests/qtest: failover: check migration with failover off tests/qtest: failover: check missing guest feature tests/qtest: failover: check the feature is correctly provided tests/qtest: failover: use a macro for check_one_card() tests/qtest: failover: clean up pathname of tests ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * More Meson conversions (0.59.x now required rather than suggested) * UMIP support for TCG x86 * Fix migration crash * Restore error output for check-block # gpg: Signature made Mon 21 Feb 2022 09:35:59 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (29 commits) configure, meson: move CONFIG_IASL to a Meson option meson, configure: move ntddscsi API check to meson meson: require dynamic linking for VSS support qga/vss-win32: require widl/midl, remove pre-built TLB file meson: do not make qga/vss-win32/meson.build conditional on C++ presence configure, meson: replace VSS SDK checks and options with --enable-vss-sdk qga/vss: use standard windows headers location qga/vss-win32: use widl if available meson: drop --with-win-sdk qga/vss-win32: fix midl arguments meson: refine check for whether to look for virglrenderer configure, meson: move guest-agent, tools to meson configure, meson: move smbd options to meson_options.txt configure, meson: move coroutine options to meson_options.txt configure, meson: move some default-disabled options to meson_options.txt meson: define qemu_cflags/qemu_ldflags configure, meson: move block layer options to meson_options.txt configure, meson: move image format options to meson_options.txt configure, meson: cleanup qemu-ga libraries configure, meson: move TPM check to meson ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21target/rx: Remove unused ENV_OFFSET definitionPhilippe Mathieu-Daudé
The last use of ENV_OFFSET was removed in 5e1401969b ("cpu: Move icount_decr to CPUNegativeOffsetState"); the commit of target/rx came in just afterward. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220203001252.37982-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-02-21target/avr: Correct AVRCPUClass docstringPhilippe Mathieu-Daudé
There is no 'vr' field in AVRCPUClass. Likely a copy/paste typo from CRISCPUClass ;) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220122001036.83267-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-02-21include: Move hardware version declarations to new qemu/hw-version.hPeter Maydell
The "hardware version" machinery (qemu_set_hw_version(), qemu_hw_version(), and the QEMU_HW_VERSION define) is used by fewer than 10 files. Move it out from osdep.h into a new qemu/hw-version.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220208200856.3558249-6-peter.maydell@linaro.org
2022-02-21target/arm: Support PAuth extension for hvfPeter Maydell
Currently we don't allow guests under hvf to use the PAuth extension, because we didn't have any special code to handle that, and therefore in arm_cpu_pauth_finalize() we will sanitize the ID_AA64ISAR1 value the guest sees to clear the PAuth related fields. Add support for this in the same way that KVM does it, by defaulting to "PAuth enabled" if the host CPU has it and allowing the user to disable it via '-cpu pauth=no' on the command line. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-7-peter.maydell@linaro.org
2022-02-21target/arm: Fix '-cpu max' for HVFPeter Maydell
Currently when using hvf we mishandle '-cpu max': we fall through to the TCG version of its initfn, which then sets a lot of feature bits that the real host CPU doesn't have. The hvf accelerator code then exposes these bogus ID register values to the guest because it doesn't check that the host really has the features. Make '-cpu host' be like '-cpu max' for hvf, as we do with kvm. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-6-peter.maydell@linaro.org
2022-02-21target/arm: Unindent unnecessary else-clausePeter Maydell
Now that the if() branch of the condition in aarch64_max_initfn() returns early, we don't need to keep the rest of the code in the function inside an else block. Remove the else, unindenting that code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-5-peter.maydell@linaro.org
2022-02-21target/arm: Make KVM -cpu max exactly like -cpu hostPeter Maydell
Currently for KVM the intention is that '-cpu max' and '-cpu host' are the same thing, but because we did this with two separate pieces of code they have got a little bit out of sync. Specifically, 'max' has a 'sve-max-vq' property, and 'host' does not. Bring the two together by having the initfn for 'max' actually call the initfn for 'host'. This will result in 'max' no longer exposing the 'sve-max-vq' property when using KVM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-4-peter.maydell@linaro.org
2022-02-21target/arm: Use aarch64_cpu_register() for 'host' CPU typePeter Maydell
Use the aarch64_cpu_register() machinery to register the 'host' CPU type. This doesn't gain us anything functionally, but it does mean that the code for initializing it looks more like that for the other CPU types, in that its initfn then doesn't need to call arm_cpu_post_init() (because aarch64_cpu_instance_init() does that for it). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-3-peter.maydell@linaro.org
2022-02-21target/arm: Move '-cpu host' code to cpu64.cPeter Maydell
Now that KVM has dropped AArch32 host support, the 'host' CPU type is always AArch64, and we can move it to cpu64.c. This move will allow us to share code between it and '-cpu max', which should behave the same as '-cpu host' when using KVM or HVF. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-2-peter.maydell@linaro.org
2022-02-21hvf: arm: Handle unknown ID registers as RES0Alexander Graf
Recent Linux versions added support to read ID_AA64ISAR2_EL1. On M1, those reads trap into QEMU which handles them as faults. However, AArch64 ID registers should always read as RES0. Let's handle them accordingly. This fixes booting Linux 5.17 guests. Cc: qemu-stable@nongnu.org Reported-by: Ivan Babrou <ivan@cloudflare.com> Signed-off-by: Alexander Graf <agraf@csgraf.de> Message-id: 20220209124135.69183-2-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21hvf: arm: Use macros for sysreg shift/maskingAlexander Graf
We are parsing the syndrome field for sysregs in multiple places across the hvf code, but repeat shift/mask operations with hard coded constants every time. This is an error prone approach and makes it harder to reason about the correctness of these operations. Let's introduce macros that allow us to unify the constants used as well as create new helpers to extract fields from the sysreg value. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Cameron Esfahani <dirty@apple.com <mailto:dirty@apple.com>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220209124135.69183-1-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé
timer_new_ns(), cpu_get_host_ticks() and NANOSECONDS_PER_SECOND are declared in "qemu/timer.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220207082756.82600-8-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-18target/ppc: Move common SPR functions out of cpu_initFabiano Rosas
Let's leave cpu_init with just generic CPU initialization and QOM-related functions. The rest of the SPR registration functions will be moved in the following patches along with the code that uses them. These are only the commonly used ones. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-28-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move check_pow and QOM macros to a headerFabiano Rosas
These will need to be accessed from other files once we move the CPUs code to separate files. The check_pow_hid0 and check_pow_hid0_74xx are too specific to be moved to a header so I'll deal with them later when splitting this code between the multiple CPU families. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-27-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move SPR registration macros to a headerFabiano Rosas
Put the SPR registration macros in a header that is accessible outside of cpu_init.c. The following patches will move CPU-specific code to separate files and will need to access it. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-26-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Expose some SPR registration helpersFabiano Rosas
The following patches will move CPU-specific code into separate files, so expose the most used SPR registration functions: register_sdr1_sprs | 22 callers register_low_BATs | 20 callers register_non_embedded_sprs | 19 callers register_high_BATs | 10 callers register_thrm_sprs | 8 callers register_usprgh_sprs | 6 callers register_6xx_7xx_soft_tlb | only 3 callers, but it helps to keep the soft TLB code consistent. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: Rename spr_tcg.h to spr_common.hFabiano Rosas
Initial intent for the spr_tcg header was to expose the spr_read|write callbacks that are only used by TCG code. However, although these routines are TCG-specific, the KVM code needs access to env->sprs which creation is currently coupled to the callback registration. We are probably not going to decouple SPR creation and TCG callback registration any time soon, so let's rename the header to spr_common to accomodate the register_*_sprs functions that will be moved out of cpu_init.c in the following patches. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-24-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Remove register_usprg3_sprsFabiano Rosas
This function registers just one SPR and has only two callers, so open code it. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-23-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Rename register_ne_601_sprsFabiano Rosas
The important part of this function is that it applies to non-embedded CPUs, not that it also applies to the 601. We removed support for the 601 anyway, so rename this function. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-22-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Reuse init_proc_745 for the 755Fabiano Rosas
The init_proc_755 function is identical to the 745 one except for the 755-specific registers. I think it is worth it to make them share code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-21-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Reuse init_proc_604 for the 604eFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-20-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Reuse init_proc_603 for the e300Fabiano Rosas
init_proc_603 is defined after init_proc_e300, so I had to move some code around to make it work. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-19-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move 604e SPR registration into a functionFabiano Rosas
This is done to improve init_proc readability and to make subsequent patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-18-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move e300 SPR registration into a functionFabiano Rosas
This is done to improve init_proc readability and to make subsequent patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-17-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move 755 L2 cache SPRs into a functionFabiano Rosas
This is just to have 755-specific registers contained into a function, intead of leaving them open-coded in init_proc_755. It makes init_proc easier to read and keeps later patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-16-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 7xx SPR registrationFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-15-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 745/755 SPR registrationFabiano Rosas
The 745 and 755 can share the HID registration, so move it all into register_755_sprs, which applies for both CPUs. Also rename that function to register_745_sprs, since the 745 is the earliest of the two. This will help with separating 755-specific registers in a subsequent patch. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-14-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 604 SPR registrationFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-13-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 603 SPR registrationFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Deduplicate 440 SPR registrationFabiano Rosas
Move some of the 440 registers that are being repeated in the 440* CPUs to register_440_sprs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Decouple 74xx SPR registration from 7xxFabiano Rosas
We're considering these two to be from different CPU families, so duplicate some code to keep them separate. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Decouple G2 SPR registration from 755Fabiano Rosas
We're considering these two to be in different CPU families (6xx and 7xx), so keep their SPR registration separate. The code was copied into register_G2_sprs and the common function was renamed to apply only to the 755. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move G2 SPRs into register_G2_sprsFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move 405 SPRs into register_405_sprsFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Avoid nested SPR register functionsFabiano Rosas
Make sure that every register_*_sprs function only has calls to spr_register* to register individual SPRs. Do not allow nesting. This makes the code easier to follow and a look at init_proc_* should suffice to know what SPRs a CPU has. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move Timebase registration into the common functionFabiano Rosas
Now that the 601 was removed, all of our CPUs have a timebase, so that can be moved into the common function. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Group registration of generic SPRsFabiano Rosas
The top level init_proc calls register_generic_sprs but also registers some other SPRs outside of that function. Let's group everything into a single place. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Remove G2LE init codeFabiano Rosas
The G2LE CPU initialization code is the same as the G2. Use the latter for both. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Remove not implemented commentsFabiano Rosas
The /* XXX : not implemented */ comments all over cpu_init are confusing and ambiguous. Do they mean not implemented by QEMU, not implemented in a specific access mode? Not implemented by the CPU? Do they apply to just the register right after or to a whole block? Do they mean we have an action to take in the future to implement these? Are they only informative? Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: Introduce a vhyp framework for nested HV supportNicholas Piggin
Introduce virtual hypervisor methods that can support a "Nested KVM HV" implementation using the bare metal 2-level radix MMU, and using HV exceptions to return from H_ENTER_NESTED (rather than cause interrupts). HV exceptions can now be raised in the TCG spapr machine when running a nested KVM HV guest. The main ones are the lev==1 syscall, the hdecr, hdsi and hisi, hv fu, and hv emu, and h_virt external interrupts. HV exceptions are intercepted in the exception handler code and instead of causing interrupts in the guest and switching the machine to HV mode, they go to the vhyp where it may exit the H_ENTER_NESTED hcall with the interrupt vector numer as return value as required by the hcall API. Address translation is provided by the 2-level page table walker that is implemented for the bare metal radix MMU. The partition scope page table is pointed to the L1's partition scope by the get_pate vhc method. Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220216102545.1808018-9-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: Add powerpc_reset_excp_state helperNicholas Piggin
This moves the logic to reset the QEMU exception state into its own function. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-8-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: add helper for books vhyp hypercall handlerNicholas Piggin
The virtual hypervisor currently always intercepts and handles hypercalls but with a future change this will not always be the case. Add a helper for the test so the logic is abstracted from the mechanism. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220216102545.1808018-7-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: make vhyp get_pate method take lpid and return successNicholas Piggin
In prepartion for implementing a full partition table option for vhyp, update the get_pate method to take an lpid and return a success/fail indicator. The spapr implementation currently just asserts lpid is always 0 and always return success. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-6-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: add vhyp addressing mode helper for radix MMUNicholas Piggin
The radix on vhyp MMU uses a single-level radix table walk, with the partition scope mapping provided by the flat QEMU machine memory. A subsequent change will use the two-level radix walk on vhyp in some situations, so provide a helper which can abstract that logic. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220216102545.1808018-5-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: raise HV interrupts for partition table entry problemsNicholas Piggin
Invalid or missing partition table entry exceptions should cause HV interrupts. HDSISR is set to bad MMU config, which is consistent with the ISA and experimentally matches what POWER9 generates. Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-2-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-16target/i386: add TCG support for UMIPGareth Webb
Signed-off-by: Gareth Webb <gareth.webb@umbralsoftware.co.uk> Message-Id: <164425598317.21902.4257759159329756142-1@git.sr.ht> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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