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AgeCommit message (Expand)Author
2017-02-24tcg: enable MTTCG by default for ARM on x86 hostsAlex Bennée
2017-02-24target-arm: ensure all cross vCPUs TLB flushes completeAlex Bennée
2017-02-24target-arm: don't generate WFE/YIELD calls for MTTCGAlex Bennée
2017-02-24target-arm/powerctl: defer cpu reset work to CPU contextAlex Bennée
2017-02-24cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée
2017-02-24tcg: drop global lock during TCG code executionJan Kiszka
2017-02-23Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170222' into stagingPeter Maydell
2017-02-21target-mips: Provide function to test if a CPU supports an ISAPaul Burton
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth
2017-02-16target-i386: correctly propagate retaddr into SVM helpersPaolo Bonzini
2017-02-16report guest crash information in GUEST_PANICKED eventAnton Nefedov
2017-02-16i386/cpu: add crash-information QOM propertyAnton Nefedov
2017-02-14Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into stagingPeter Maydell
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson
2017-02-14target/openrisc: Fix maddRichard Henderson
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Implement msyncRichard Henderson
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson
2017-02-14target/openrisc: Set flags on helpersRichard Henderson
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson
2017-02-13migration: consolidate VMStateField.startHalil Pasic
2017-02-10target-arm: Enable vPMU support under TCG modeWei Huang
2017-02-10target-arm: Add support for PMU register PMINTENSET_EL1Wei Huang
2017-02-10target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0Wei Huang
2017-02-10target-arm: Add support for PMU register PMSELR_EL0Wei Huang
2017-02-07target/arm: A32, T32: Create Instruction Syndromes for Data AbortsPeter Maydell
2017-02-07target/arm: Abstract out pbit/wbit tests in ARM ldr/str decodePeter Maydell
2017-02-07arm: Correctly handle watchpoints for BE32 CPUsJulian Brown
2017-02-07Fix Thumb-1 BE32 execution and disassembly.Julian Brown
2017-02-07target/arm: Add cfgend parameter for ARM CPU selection.Julian Brown
2017-02-06target/hppa: Fix gdb_write_registerRichard Henderson
2017-02-06target/hppa: Tidy do_cbranchRichard Henderson
2017-02-02Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into...Peter Maydell
2017-02-02ppc/kvm: Handle the "family" CPU via alias instead of registering new typesThomas Huth
2017-02-02target/ppc/mmu_hash64: Fix incorrect shift value in amr calculationSuraj Jitindar Singh
2017-02-02target/ppc/mmu_hash64: Fix printing unsigned as signed intSuraj Jitindar Singh
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