aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2019-03-15target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif
2019-03-15target/arm: change arch timer registers access permissionDongjiu Geng
2019-03-13Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...Peter Maydell
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann
2019-03-12target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle
2019-03-12target/hppa: add TLB protection id checkSven Schnelle
2019-03-12target/hppa: allow multiple itlbp without itlbaSven Schnelle
2019-03-12target/hppa: fix b,gate instructionSven Schnelle
2019-03-12target/hppa: ignore DIAG opcodeSven Schnelle
2019-03-12target/hppa: remove PSW I/R/Q bit checkSven Schnelle
2019-03-12target/hppa: add TLB trace eventsSven Schnelle
2019-03-12target/hppa: report ITLB_EXCP_MISS for ITLB missesSven Schnelle
2019-03-12target/hppa: fix TLB handling for page 0Sven Schnelle
2019-03-12target/hppa: fix overwriting source reg in addbSven Schnelle
2019-03-12target/hppa: Check for page crossings in use_goto_tbRichard Henderson
2019-03-12spapr: Use CamelCase properlyDavid Gibson
2019-03-12target/ppc: Optimize x[sv]xsigdp using deposit_i64()Philippe Mathieu-Daudé
2019-03-12target/ppc: Optimize xviexpdp() using deposit_i64()Philippe Mathieu-Daudé
2019-03-12target/ppc: add HV support for POWER9Cédric Le Goater
2019-03-12target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_c...Mark Cave-Ayland
2019-03-12target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian...Mark Cave-Ayland
2019-03-12target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr...Mark Cave-Ayland