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2021-09-01target/arm: Implement MVE FP max/min across vectorPeter Maydell
Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These calculate the maximum or minimum of floating point elements across a vector, starting with a value in a general purpose register and returning the result there. The pseudocode silences a possible SNaN in the accumulating result on every iteration (by calling FPConvertNaN), but we do it only on the input ra, because if none of the inputs to float*_maxnum or float*_minnum are SNaNs then the result can't be an SNaN. Note that we can't use the float*_maxnuma() etc functions we defined earlier for VMAXNMA and VMINNMA, because we mustn't take the absolute value of the starting general-purpose register value, which could be negative. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-01target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell
Implement the MVE fp-with-scalar VFMA and VFMAS insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-01target/arm: Implement MVE scalar fp insnsPeter Maydell
Implement the MVE scalar floating point insns VADD, VSUB and VMUL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-01target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell
Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but the destination register must be the same as one of the source registers. We defer the decode of the size in bit 28 to the individual insn patterns rather than doing it in the format, because otherwise we would have a single insn pattern that overlapped with two groups (eg VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn patterns per insn seems clearer than a complex multilevel nesting of overlapping and non-overlapping groups. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VCMUL and VCMLAPeter Maydell
Implement the MVE VCMUL and VCMLA insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VFMA and VFMSPeter Maydell
Implement the MVE VFMA and VFMS insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VCADDPeter Maydell
Implement the MVE VCADD insn. Note that here the size bit is the opposite sense to the other 2-operand fp insns. We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case, because that would mean we can't use the DO_2OP_FP macro in translate-mve.c. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell
Implement more simple 2-operand floating point MVE insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/arm: Implement MVE VADD (floating-point)Peter Maydell
Implement the MVE VADD (floating-point) insn. Handling of this is similar to the 2-operand integer insns, except that we must take care to only update the floating point exception status if the least significant bit of the predicate mask for each element is active. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson
Remove gen_get_gpr, as the function becomes unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-25-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson
Exit early if check_access fails. Split out do_hlv, do_hsv, do_hlvx subroutines. Use dest_gpr, get_gpr in the new subroutines. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-24-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-23-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-22-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson
Always use tcg_gen_deposit_z_tl; the special case for shamt >= 32 is handled there. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-21-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-20-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson
We failed to write into *val for these read functions; replace them with read_zero. Only warn about unsupported non-zero value when writing a non-zero value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-18-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson
We distinguish write-only by passing ret_value as NULL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-17-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson
Narrow the scope of t0 in trans_jalr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson
These operations can be done in one instruction on some hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
These operations are greatly simplified by ctx->w, which allows us to fold gen_shiftw into gen_shift. Split gen_shifti into gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
Use ctx->w for ctpopw, which is the only one that can re-use the generic algorithm for the narrow operation. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
Move these helpers near their use by the trans_* functions within insn_trans/trans_rvb.c.inc. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
Move these helpers near their use by the trans_* functions within insn_trans/trans_rvm.c.inc. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson
Split out gen_mulh and gen_mulhu and use the common helper. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
Use ctx->w and the enhanced gen_arith function. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
Most arithmetic does not require extending the inputs. Exceptions include division, comparison and minmax. Begin using ctx->w, which allows elimination of gen_addw, gen_subw, gen_mulw. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-7-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson
Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force tcg globals into temps, returning a constant 0 for $zero as source and a new temp for $zero as destination. Introduce ctx->w for simplifying word operations, such as addw. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
We will require the context to handle RV64 word operations. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Clean up division helpersRichard Henderson
Utilize the condition in the movcond more; this allows some of the setcond that were feeding into movcond to be removed. Do not write into source1 and source2. Re-name "condN" to "tempN" and use the temporaries for more than holding conditions. Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
Replace uses of tcg_const_* with the allocate and free close together. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-2-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei
For U-mode CSRs, read-only check is also needed. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei
For some cpu, the isa version has already been set in cpu init function. Thus only override the isa version when isa version is not set, or users set different isa version explicitly by cpu parameters. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng
When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned, not -1 (RISCV_EXCP_NONE). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-27Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827' ↵Peter Maydell
into staging ppc patch queue 2021-08-27 First ppc pull request for qemu-6.2. As usual, there's a fair bit here, since it's been queued during the 6.1 freeze. Highlights are: * Some fixes for 128 bit arithmetic and some vector opcodes that use them * Significant improvements to the powernv to support POWER10 cpus (more to come though) * Several cleanups to the ppc softmmu code * A few other assorted fixes # gpg: Signature made Fri 27 Aug 2021 08:09:12 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.2-20210827: target/ppc: fix vector registers access in gdbstub for little-endian include/qemu/int128.h: introduce bswap128s target/ppc: fix vextu[bhw][lr]x helpers include/qemu/int128.h: define struct Int128 according to the host endianness ppc/xive: Export xive_presenter_notify() ppc/xive: Export PQ get/set routines ppc/pnv: add a chip topology index for POWER10 ppc/pnv: Distribute RAM among the chips ppc/pnv: Use a simple incrementing index for the chip-id ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode ppc/pnv: Change the POWER10 machine to support DD2 only ppc: Add a POWER10 DD2 CPU ppc/pnv: update skiboot to commit 820d43c0a775. target/ppc: moved store_40x_sler to helper_regs.c target/ppc: moved ppc_store_sdr1 to mmu_common.c target/ppc: divided mmu_helper.c in 2 files spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree xive: Remove extra '0x' prefix in trace events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-27Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2021-08-26' ↵Peter Maydell
into staging Error reporting patches for 2021-08-26 # gpg: Signature made Thu 26 Aug 2021 16:17:05 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2021-08-26: vl: Clean up -smp error handling Remove superfluous ERRP_GUARD() vhost: Clean up how VhostOpts method vhost_backend_init() fails vhost: Clean up how VhostOpts method vhost_get_config() fails microvm: Drop dead error handling in microvm_machine_state_init() migration: Handle migration_incoming_setup() errors consistently migration: Unify failure check for migrate_add_blocker() whpx nvmm: Drop useless migrate_del_blocker() vfio: Avoid error_propagate() after migrate_add_blocker() i386: Never free migration blocker objects instead of sometimes vhost-scsi: Plug memory leak on migrate_add_blocker() failure multi-process: Fix pci_proxy_dev_realize() error handling spapr: Explain purpose of ->fwnmi_migration_blocker more clearly spapr: Plug memory leak when we can't add a migration blocker error: Use error_fatal to simplify obvious fatal errors (again) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-27target/ppc: fix vector registers access in gdbstub for little-endianMatheus Ferst
As vector registers are stored in host endianness, we shouldn't swap its 64-bit elements in user mode. Add a 16-byte case in ppc_maybe_bswap_register to handle the reordering of elements in softmmu and remove avr_need_swap which is now unused. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826145656.2507213-3-matheus.ferst@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27target/ppc: fix vextu[bhw][lr]x helpersMatheus Ferst
These helpers shouldn't depend on the host endianness, as they only use shifts, ands, and int128_* methods. Fixes: 60caf2216bf0 ("target-ppc: add vextu[bhw][lr]x instructions") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826141446.2488609-3-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering ↵Cédric Le Goater
power-saving mode The Hypervisor Decrementer exception should not be generated while the CPU is in power-saving mode (see cpu_ppc_hdecr_excp()). However, discarding the exception before entering the power-saving mode is wrong since we would loose a previously generated HDEC. Fixes: 4b236b621bf0 ("ppc: Initial HDEC support") Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27ppc: Add a POWER10 DD2 CPUCédric Le Goater
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have HAIL but since it does not break the modeling and that we don't plan to support DD1, modify the LPCR mask of all the POWER10 family. Setting the HAIL bit is a requirement to support the scv instruction on PowerNV POWER10 platforms since glibc-2.33. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27target/ppc: moved store_40x_sler to helper_regs.cLucas Mateus Castro (alqotel)
moved store_40x_sler from mmu_common.c to helper_regs.c as it is a function to store a value in a special purpose register, so moving it to a file focused in special register manipulation is more appropriate. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210723175627.72847-4-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27target/ppc: moved ppc_store_sdr1 to mmu_common.cLucas Mateus Castro (alqotel)
ppc_store_sdr1 was at first in mmu_helper.c and was moved as part the patches to enable the disable-tcg option, now it's being moved back to a file that will be compiled with that option Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210723175627.72847-3-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27target/ppc: divided mmu_helper.c in 2 filesLucas Mateus Castro (alqotel)
Divided mmu_helper.c in 2 files, functions inside #ifdef CONFIG_SOFTMMU stayed in mmu_helper.c, other functions moved to mmu_common.c. Updated meson.build to compile mmu_common.c and only compile mmu_helper.c when CONFIG_TCG is set. Moved function declarations, #define and structs used by both files to internal.h except for functions that use structures defined in cpu.h, those were moved to cpu.h. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210723175627.72847-2-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-26target/arm: Do hflags rebuild in cpsr_write()Peter Maydell
Currently we rely on all the callsites of cpsr_write() to rebuild the cached hflags if they change one of the CPSR bits which we use as a TB flag and cache in hflags. This is a bit awkward when we want to change the set of CPSR bits that we cache, because it means we need to re-audit all the cpsr_write() callsites to see which flags they are writing and whether they now need to rebuild the hflags. Switch instead to making cpsr_write() call arm_rebuild_hflags() itself if one of the bits being changed is a cached bit. We don't do the rebuild for the CPSRWriteRaw write type, because that kind of write is generally doing something special anyway. For the CPSRWriteRaw callsites in the KVM code and inbound migration we definitely don't want to recalculate the hflags; the callsites in boot.c and arm-powerctl.c have to do a rebuild-hflags call themselves anyway because of other CPU state changes they make. This allows us to drop explicit arm_rebuild_hflags() calls in a couple of places where the only reason we needed to call it was the CPSR write. This fixes a bug where we were incorrectly failing to rebuild hflags in the code path for a gdbstub write to CPSR, which meant that you could make QEMU assert by breaking into a running guest, altering the CPSR to change the value of, for example, CPSR.E, and then continuing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210817201843.3829-1-peter.maydell@linaro.org
2021-08-26target/arm: Implement HSTR.TJDBXPeter Maydell
In v7A, the HSTR register has a TJDBX bit which traps NS EL0/EL1 access to the JOSCR and JMCR trivial Jazelle registers, and also BXJ. Implement these traps. In v8A this HSTR bit doesn't exist, so don't trap for v8A CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210816180305.20137-3-peter.maydell@linaro.org
2021-08-26target/arm: Implement HSTR.TTEEPeter Maydell
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses to the Thumb2EE TEECR and TEEHBR registers to be trapped to the hypervisor. Implement these traps. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
2021-08-26target/arm: Avoid assertion trying to use KVM and multiple ASesPeter Maydell
KVM cannot support multiple address spaces per CPU; if you try to create more than one then cpu_address_space_init() will assert. In the Arm CPU realize function, detect the configurations which would cause us to need more than one AS, and cleanly fail the realize rather than blundering on into the assertion. This turns this: $ qemu-system-aarch64 -enable-kvm -display none -cpu max -machine raspi3b qemu-system-aarch64: ../../softmmu/physmem.c:747: cpu_address_space_init: Assertion `asidx == 0 || !kvm_enabled()' failed. Aborted into: $ qemu-system-aarch64 -enable-kvm -display none -machine raspi3b qemu-system-aarch64: Cannot enable KVM when guest CPU has EL3 enabled and this: $ qemu-system-aarch64 -enable-kvm -display none -machine mps3-an524 qemu-system-aarch64: ../../softmmu/physmem.c:747: cpu_address_space_init: Assertion `asidx == 0 || !kvm_enabled()' failed. Aborted into: $ qemu-system-aarch64 -enable-kvm -display none -machine mps3-an524 qemu-system-aarch64: Cannot enable KVM when using an M-profile guest CPU Fixes: https://gitlab.com/qemu-project/qemu/-/issues/528 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210816135842.25302-3-peter.maydell@linaro.org
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell
arch_init.h only defines the QEMU_ARCH_* enumeration and the arch_type global. Don't include it in files that don't use those. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210730105947.28215-8-peter.maydell@linaro.org
2021-08-26target/arm/cpu64: Validate sve vector lengths are supportedAndrew Jones
Future CPU types may specify which vector lengths are supported. We can apply nearly the same logic to validate those lengths as we do for KVM's supported vector lengths. We merge the code where we can, but unfortunately can't completely merge it because KVM requires all vector lengths, power-of-two or not, smaller than the maximum enabled length to also be enabled. The architecture only requires all the power-of-two lengths, though, so TCG will only enforce that. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823160647.34028-5-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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