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2021-11-02target/arm: Use tcg_constant_i32() in op_smlad()Philippe Mathieu-Daudé
Avoid using a TCG temporary for a read-only constant. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211029231834.2476117-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/arm: Advertise MVE to gdb when presentPeter Maydell
Cortex-M CPUs with MVE should advertise this fact to gdb, using the org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR register. Presence of this feature also tells gdb to create pseudo-registers Q0..Q7, so we do not need to tell gdb about them separately. Note that unless you have a very recent GDB that includes this fix: http://patches-tcwg.linaro.org/patch/58133/ gdb will mis-print the individual fields of the VPR register as zero (but showing the whole thing as hex, eg with "print /x $vpr" will give the correct value). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211101160814.5103-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02monitor: remove 'info ioapic' HMP commandDaniel P. Berrangé
This command was turned into a no-op four years ago in commit 0c8465440d50c18a7bb13d0a866748f0593e193a Author: Peter Xu <peterx@redhat.com> Date: Fri Dec 29 15:31:04 2017 +0800 hmp: obsolete "info ioapic" Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02KVM: SVM: add migration support for nested TSC scalingMaxim Levitsky
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com> Message-Id: <20211101132300.192584-4-mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-02target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPUPhilippe Mathieu-Daudé
FCR0_HAS2008 flag has been enabled in commit ba5c79f2622 ("target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs"), so remove the obsolete FIXME comment. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028212103.2126176-1-f4bug@amsat.org>
2021-11-02target/mips: Fix Loongson-3A4000 MSAIR config registerPhilippe Mathieu-Daudé
When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12, so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000 CPU model added in commit af868995e1b. Cc: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026180920.1085516-1-f4bug@amsat.org>
2021-11-02target/mips: Remove one MSA unnecessary decodetree overlap groupPhilippe Mathieu-Daudé
Only the MSA generic opcode was overlapping with the other instructions. Since the previous commit removed it, we can now remove the overlap group. The decodetree script forces us to re-indent the opcodes. Diff trivial to review using `git-diff --ignore-all-space`. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-32-f4bug@amsat.org>
2021-11-02target/mips: Remove generic MSA opcodePhilippe Mathieu-Daudé
All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-31-f4bug@amsat.org>
2021-11-02target/mips: Convert CTCMSA opcode to decodetreePhilippe Mathieu-Daudé
Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-30-f4bug@amsat.org>
2021-11-02target/mips: Convert CFCMSA opcode to decodetreePhilippe Mathieu-Daudé
Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA MOVE.V opcode to decodetreePhilippe Mathieu-Daudé
Convert the MOVE.V opcode (Vector Move) to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-28-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA COPY_S and INSERT opcodes to decodetreePhilippe Mathieu-Daudé
Convert the COPY_S (Element Copy to GPR Signed) opcode and INSERT (GPR Insert Element) opcode to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-27-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA COPY_U opcode to decodetreePhilippe Mathieu-Daudé
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree. Since the 'n' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-26-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA ELM instruction format to decodetreePhilippe Mathieu-Daudé
Convert instructions with an immediate element index and data format df/n to decodetree. Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-25-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)Philippe Mathieu-Daudé
Convert 3-register operations to decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-24-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)Philippe Mathieu-Daudé
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)Philippe Mathieu-Daudé
Convert 3-register operations to decodetree. Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), these instructions are not defined for the BYTE format. Therefore the TRANS_DF_iii_b() macro returns 'false' in that case, because no such instruction is decoded. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-22-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)Philippe Mathieu-Daudé
Convert 3-register operations to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Note, the format definition could be named @3rf_b (for 3R with a df field BYTE-based) but since the instruction class is named '3R', we simply call the format @3r to ease reviewing the msa.decode file. However we directly call the trans_msa_3rf() function, which handles the BYTE-based df field. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-21-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé
Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-20-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé
Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-19-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé
Convert 3-register instructions with implicit data formats to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-18-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé
Convert 2-register operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-17-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé
Convert the FILL opcode (Vector Fill from GPR) to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé
Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-15-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé
Convert load/store instructions to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-14-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé
Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-13-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-12-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé
Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-11-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé
Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-10-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé
Convert the LDI opcode (Immediate Load) to decodetree. Since it overlaps with the generic MSA handler, use a decodetree overlap group. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-9-f4bug@amsat.org>
2021-11-02target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé
This 'shift amount' format is not always 16-bit, so name it generically as 'sa'. This will help to unify the various arg_msa decodetree generated structures. Rename the @bz format -> @bz_v (specific @bz with df=3) and @bz_df -> @bz (generic @bz). Since we modify &msa_bz, re-align its arguments, so the other structures added in the following commits stay visually aligned. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-8-f4bug@amsat.org>
2021-11-02target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé
Replace magic DataFormat value by the corresponding enum from CPUMIPSMSADataFormat. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-7-f4bug@amsat.org>
2021-11-02target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé
Have check_msa_access() return a boolean value so we can return early if MSA is not enabled (the instruction got decoded properly, but we raised an exception). Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-6-f4bug@amsat.org>
2021-11-02target/mips: Use dup_const() to simplifyPhilippe Mathieu-Daudé
The dup_const() helper makes the code easier to follow, use it. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-5-f4bug@amsat.org>
2021-11-02target/mips: Adjust style in msa_translate_init()Philippe Mathieu-Daudé
While the first 'off' variable assignment is unused, it helps to better understand the code logic. Move the assignation where it would have been used so it is easier to compare the MSA registers based on FPU ones versus the MSA specific registers. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211023214803.522078-34-f4bug@amsat.org>
2021-11-02target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé
The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-3-f4bug@amsat.org>
2021-11-02target/mips: Fix MSA MADDV.B opcodePhilippe Mathieu-Daudé
The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-2-f4bug@amsat.org>
2021-11-02target/sparc: Set fault address in sparc_cpu_do_unaligned_accessRichard Henderson
We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sparc: Split out build_sfsrRichard Henderson
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sparc: Remove DEBUG_UNALIGNEDRichard Henderson
The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sh4: Set fault address in superh_cpu_do_unaligned_accessRichard Henderson
We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/s390x: Implement s390x_cpu_record_sigbusRichard Henderson
For s390x, the only unaligned accesses that are signaled are atomic, and we don't actually want to raise SIGBUS for those, but instead raise a SPECIFICATION error, which the kernel will report as SIGILL. Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemuRichard Henderson
This is not used by, nor required by, user-only. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/ppc: Set fault address in ppc_cpu_do_unaligned_accessRichard Henderson
We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-ppc@nongnu.org Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/ppc: Move SPR_DSISR setting to powerpc_excpRichard Henderson
By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/microblaze: Do not set MO_ALIGN for user-onlyRichard Henderson
The kernel will fix up unaligned accesses, so emulate that by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/arm: Implement arm_cpu_record_sigbusRichard Henderson
Because of the complexity of setting ESR, re-use the existing arm_cpu_do_unaligned_access function. This means we have to handle the exception ourselves in cpu_loop, transforming it to the appropriate signal. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/alpha: Implement alpha_cpu_record_sigbusRichard Henderson
Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/xtensa: Make xtensa_cpu_tlb_fill sysemu onlyRichard Henderson
The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sparc: Make sparc_cpu_tlb_fill sysemu onlyRichard Henderson
The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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