aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2020-06-26target/arm: Add MTE system registersRichard Henderson
2020-06-26target/arm: Add DISAS_UPDATE_NOCHAINRichard Henderson
2020-06-26target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXITRichard Henderson
2020-06-26target/arm: Add support for MTE to HCR_EL2 and SCR_EL3Richard Henderson
2020-06-26target/arm: Add support for MTE to SCTLR_ELxRichard Henderson
2020-06-26target/arm: Improve masking of SCR RES0 bitsRichard Henderson
2020-06-26target/arm: Add isar tests for mteRichard Henderson
2020-06-26Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200626' into...Peter Maydell
2020-06-26target/ppc: Remove TIDR from POWER10 processorCédric Le Goater
2020-06-25Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into stagingPeter Maydell
2020-06-23target/arm: Check supported KVM features globally (not per vCPU)Philippe Mathieu-Daudé
2020-06-23target/arm: Remove dead code relating to SABA and UABAPeter Maydell
2020-06-23target/arm: Remove unnecessary gen_io_end() callsPeter Maydell
2020-06-23target/arm: Move some functions used only in translate-neon.inc.c to that filePeter Maydell
2020-06-23target/arm: Convert Neon VTRN to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon VSWP to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc VCVT insns to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc VRINT insns to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetreePeter Maydell
2020-06-23target/arm: Convert simple fp Neon 2-reg-misc insnsPeter Maydell
2020-06-23target/arm: Convert Neon VQABS, VQNEG to decodetreePeter Maydell
2020-06-23target/arm: Convert remaining simple 2-reg-misc Neon opsPeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetreePeter Maydell
2020-06-23target/arm: Make gen_swap_half() take separate src and destPeter Maydell
2020-06-23target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefsPeter Maydell
2020-06-23target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFnPeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc crypto operations to decodetreePeter Maydell
2020-06-23target/arm: Convert vectorised 2-reg-misc Neon ops to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon VCVT f16/f32 insns to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc VSHLL to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon narrowing moves to decodetreePeter Maydell
2020-06-23target/arm: Convert VZIP, VUZP to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc pairwise ops to decodetreePeter Maydell
2020-06-23target/arm: Convert Neon 2-reg-misc VREV64 to decodetreePeter Maydell
2020-06-22target/xtensa: drop gen_io_end callMax Filippov
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng
2020-06-19riscv: Add helper to make NaN-boxing for FP registerIan Jiang
2020-06-18vfio-ccw: Add support for the schib regionFarhan Ali
2020-06-16Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200616'...Peter Maydell
2020-06-16Merge remote-tracking branch 'remotes/armbru/tags/pull-qom-2020-06-15' into s...Peter Maydell