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2018-01-11Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell
staging qemu-sparc update # gpg: Signature made Tue 09 Jan 2018 22:12:22 GMT # gpg: using RSA key 0x5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: (25 commits) sun4u_iommu: add trace event for IOMMU translations sun4u_iommu: convert from IOMMU_DPRINTF to trace-events sun4u_iommu: update to reflect IOMMU is no longer part of the APB device sun4u: split IOMMU device out from apb.c to sun4u_iommu.c apb: QOMify IOMMU sun4m: remove include/hw/sparc/sun4m.h and all references to it sun4m: move IOMMU declarations from sun4m.h to sun4m_iommu.h sun4m: move sun4m_iommu.c from hw/dma to hw/sparc sun4u: switch from EBUS_DPRINTF() macro to trace-events sparc64: introduce trace-events for hw/sparc64 apb: replace OBIO interrupt numbers in pci_pbmA_map_irq() with constants ebus: wire up OBIO interrupts to APB pbm via qdev GPIOs apb: remove busA property from PBMPCIBridge state apb: split pci_pbm_map_irq() into separate functions for bus A and bus B apb: remove pci_apb_init() and instantiate APB device using qdev apb: move the two secondary PCI bridges objects into APBState apb: use gpios to wire up the apb device to the SPARC CPU IRQs apb: return APBState from pci_apb_init() rather than PCIBus apb: APB QOMify tidy-up sun4u: move initialisation of all ISABus devices into ebus_realize() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-09target/sparc: remove MemoryRegionSection check code from ↵Jean-Christophe Dubois
sparc_cpu_get_phys_page_debug() This code is preventing the MMU debug code from displaying virtual mappings of IO devices (anything that is not located in the RAM). Before this patch, Qemu would output 0xffffffffffffffff (-1) as the physical address corresponding to an IO device virtual address. With this patch the intended physical address is displayed. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-01-09Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into stagingPeter Maydell
target/xtensa updates: - add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. # gpg: Signature made Tue 09 Jan 2018 18:11:02 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180109-xtensa: target/xtensa: implement disassembler target/xtensa: implement const16 target/xtensa: implement GPIO32 target/xtensa: implement salt/saltu target/xtensa: add internal/noop SRs and opcodes target/xtensa: drop DisasContext::litbase target/xtensa: tests: fix memctl SR test target/xtensa: use libisa for instruction decoding target/xtensa: switch fsf to libisa target/xtensa: switch dc233c to libisa target/xtensa: switch dc232b to libisa target/xtensa: update import_core.sh script for libisa target/xtensa: extract FPU2000 opcode translators target/xtensa: extract core opcode translators target/xtensa: import libisa source target/xtensa: pass actual frame size to the entry helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-09target/xtensa: implement disassemblerMax Filippov
Add disas/xtensa.c and use libisa for instruction decoding/opcode name lookup. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement const16Max Filippov
const16 is an opcode that shifts 16 lower bits of an address register to the 16 upper bits and puts its immediate operand into the lower 16 bits. It is not controlled by an Xtensa option and doesn't have a fixed opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement GPIO32Max Filippov
GPIO32 is not in the core ISA, but it was widely used in Diamond Cores. This implementation doesn't do actual I/O and doesn't handle the case of GPIO32 state being a part of coprocessor. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement salt/saltuMax Filippov
SALT/SALTU are recent additions to the core Xtensa ISA that do signed/unsigned setcond. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: add internal/noop SRs and opcodesMax Filippov
Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: drop DisasContext::litbaseMax Filippov
It doesn't help much, always-set bit 0 of the LITBASE SR is easy to compensate with decrement of the l32r immediate argument. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: use libisa for instruction decodingMax Filippov
Replace manual opcode analysis with libisa-based code. This makes it possible to support variable-encoding instructions of the core ISA, like const16, and will allow to support advanced Xtensa features, like FLIX and TIE. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-08Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Thu 04 Jan 2018 16:37:32 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: fix m68k_cpu_dump_state() target/m68k: add the Interrupt Stack Pointer target/m68k: add andi/ori/eori to SR/CCR target/m68k: add 680x0 "move to SR" instruction target/m68k: move CCR/SR functions target/m68k: implement fsave/frestore target/m68k: add reset target/m68k: add cpush/cinv target/m68k: softmmu cleanup target/m68k: add move16 target/m68k: add chk and chk2 target/m68k: manage 680x0 stack frames target/m68k: add CPU_LOG_INT trace target/m68k: use insn_pc to generate instruction fault address linux-user, m68k: correctly manage SR in context target/m68k: fix gen_get_ccr() target-m68k: sync CC_OP before gen_jmp_tb() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-08Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171229' into stagingPeter Maydell
Queued TCG patches # gpg: Signature made Fri 29 Dec 2017 20:44:06 GMT # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20171229: tcg: add cs_base and flags to -d exec output tcg: Allow 6 arguments to TCG helpers tcg: Add tcg_signed_cond tcg: Generalize TCGOp parameters tcg: Dynamically allocate TCGOps tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* target/moxie: Fix tlb_fill target/*helper: don't check retaddr before calling cpu_restore_state Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-08Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-hvf' into ↵Peter Maydell
staging Initial support for the HVF accelerator # gpg: Signature made Sat 23 Dec 2017 07:51:18 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream-hvf: i386: hvf: cleanup x86_gen.h i386: hvf: remove VM_PANIC from "in" i386: hvf: remove addr_t i386: hvf: simplify flag handling i386: hvf: abort on decoding error i386: hvf: remove ZERO_INIT macro i386: hvf: remove more dead emulator code i386: hvf: unify register enums between HVF and the rest i386: hvf: header cleanup i386: hvf: move all hvf files in the same directory i386: hvf: inject General Protection Fault when vmexit through vmcall i386: hvf: refactor event injection code for hvf i386: hvf: implement vga dirty page tracking i386: refactor KVM cpuid code so that it applies to hvf as well i386: hvf: implement hvf_get_supported_cpuid i386: hvf: use new helper functions for put/get xsave i386: hvf: fix licensing issues; isolate task handling code (GPL v2-only) i386: hvf: add code base from Google's QEMU repository apic: add function to apic that will be used by hvf Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-04target/m68k: fix m68k_cpu_dump_state()Laurent Vivier
Display correctly the Trace bits for 680x0 (2 bits instead of 1 for Coldfire). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-18-laurent@vivier.eu>
2018-01-04target/m68k: add the Interrupt Stack PointerLaurent Vivier
Add the third stack pointer, the Interrupt Stack Pointer (ISP) (680x0 only). This stack will be needed in softmmu mode. Update movec to set/get the value of the three stacks. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-17-laurent@vivier.eu>
2018-01-04target/m68k: add andi/ori/eori to SR/CCRLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-16-laurent@vivier.eu>
2018-01-04target/m68k: add 680x0 "move to SR" instructionLaurent Vivier
Some cleanup, and allows SR to be moved from any addressing mode. Previous code was wrong for coldfire: coldfire also allows to use addressing mode to set SR/CCR. It only supports Data register to get SR/CCR (move from) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-15-laurent@vivier.eu>
2018-01-04target/m68k: move CCR/SR functionsLaurent Vivier
The following patches will be clearer if we move functions before adding new ones. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-14-laurent@vivier.eu>
2018-01-04target/m68k: implement fsave/frestoreLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-13-laurent@vivier.eu>
2018-01-04target/m68k: add resetLaurent Vivier
The instruction traps if the CPU is not in Supervisor state but the helper is empty because there is no easy way to reset all the peripherals without resetting the CPU itself. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-12-laurent@vivier.eu>
2018-01-04target/m68k: add cpush/cinvLaurent Vivier
Add cache lines invalidate and cache lines push as no-op operations, as we don't have cache. These instructions are 68040 only. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-11-laurent@vivier.eu>
2018-01-04target/m68k: softmmu cleanupLaurent Vivier
don't compile supervisor only instructions in linux-user mode Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-10-laurent@vivier.eu>
2018-01-04target/m68k: add move16Laurent Vivier
move16 moves the source line to the destination line. Lines are aligned to 16-byte boundaries and are 16 bytes long. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-9-laurent@vivier.eu>
2018-01-04target/m68k: add chk and chk2Laurent Vivier
chk and chk2 compare a value to boundaries, and trigger a CHK exception if the value is out of bounds. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-8-laurent@vivier.eu>
2018-01-04target/m68k: manage 680x0 stack framesLaurent Vivier
680x0 manages several stack frame formats: - format 0: four-word stack frame - format 1: four-word throwaway stack frame - format 2: six-word stack frame - format 3: Floating-Point post-instruction stack frame - format 4: eight-word stack frame - format 7: access-error stack frame Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-7-laurent@vivier.eu>
2018-01-04target/m68k: add CPU_LOG_INT traceLaurent Vivier
Display the interrupts/exceptions information in QEMU logs (-d int) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-6-laurent@vivier.eu>
2018-01-04target/m68k: use insn_pc to generate instruction fault addressLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-5-laurent@vivier.eu>
2018-01-04target/m68k: fix gen_get_ccr()Laurent Vivier
As gen_helper_get_ccr() is able to compute CCR from cc_op and flags, we don't need to flush flags before to call it. flush_flags() and get_ccr() use COMPUTE_CCR() to compute flags. get_ccr() computes CCR value, whereas flush_flags update live cc_op and flags. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-3-laurent@vivier.eu>
2018-01-04target-m68k: sync CC_OP before gen_jmp_tb()Laurent Vivier
And remove update_cc_op() from gen_exception() because there is one in gen_jmp_im(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-2-laurent@vivier.eu>
2017-12-29tcg: Dynamically allocate TCGOpsRichard Henderson
With no fixed array allocation, we can't overflow a buffer. This will be important as optimizations related to host vectors may expand the number of ops used. Use QTAILQ to link the ops together. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson
These are now trivial sets and tests against NULL. Unwrap. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-27target/moxie: Fix tlb_fillRichard Henderson
We should not exit unless moxie_cpu_handle_mmu_fault has failed. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-27target/*helper: don't check retaddr before calling cpu_restore_stateAlex Bennée
cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [rth: Fixed up comment indentation. Added second hunk to script to combine cpu_restore_state and cpu_loop_exit.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-22i386: hvf: cleanup x86_gen.hPaolo Bonzini
This only includes VM_PANIC now. No need to include it from headers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: remove VM_PANIC from "in"Paolo Bonzini
Just give the obvious meaning to a 64-bit port, even though it should not really happen. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: remove addr_tPaolo Bonzini
Use target_ulong for virtual addresses and uint64_t for physical addresses. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: simplify flag handlingPaolo Bonzini
Remove much indirection and duplicate code, and provide a cleaner interface out of x86_flags.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: abort on decoding errorPaolo Bonzini
Rather than unsupported situations, some VM_PANIC calls actually are caused by internal errors. Convert them to just abort. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: remove ZERO_INIT macroPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: remove more dead emulator codePaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: unify register enums between HVF and the restPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: header cleanupPaolo Bonzini
Remove inclusions of system headers and avoid "pragma once". Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: move all hvf files in the same directoryPaolo Bonzini
Just call it hvf/, no need for the "utils" suffix. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: inject General Protection Fault when vmexit through vmcallSergio Andres Gomez Del Real
This patch injects a GP fault when the guest vmexit's by executing a vmcall instruction. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-15-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: refactor event injection code for hvfSergio Andres Gomez Del Real
This patch refactors the event-injection code for hvf by using the appropriate fields already provided by CPUX86State. At vmexit, it fills these fields so that hvf_inject_interrupts can just retrieve them without calling into hvf. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-14-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: implement vga dirty page trackingSergio Andres Gomez Del Real
This patch implements setting the tracking of dirty vga pages, using hvf's interface to protect guest memory. It uses the MemoryListener callback mechanism through .log_start/stop/sync Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-13-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: refactor KVM cpuid code so that it applies to hvf as wellSergio Andres Gomez Del Real
This patch generalizes some code in cpu.c for hypervisor-based accelerators, calling the new hvf_get_supported_cpuid where KVM used kvm_get_supported_cpuid. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-12-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: implement hvf_get_supported_cpuidSergio Andres Gomez Del Real
This patch implements hvf_get_supported_cpuid, which returns the set of features supported by both the host processor and the hypervisor. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-11-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: use new helper functions for put/get xsaveSergio Andres Gomez Del Real
This patch makes use of the helper functions for handling xsave in xsave_helper.c, which are shared with kvm. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-10-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-22i386: hvf: fix licensing issues; isolate task handling code (GPL v2-only)Sergio Andres Gomez Del Real
This patch replaces the license header for those files that were either GPL v2-or-v3, or GPL v2-only; the replacing license is GPL v2-or-later. The code for task switching/handling, which is derived from KVM and hence is GPL v2-only, is isolated in the new files (with this license) x86_task.c/.h, and the corresponding compilation rule is added to target/i386/hvf-utils/Makefile.objs. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-4-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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