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2021-01-14target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé
Some FPU / Coprocessor translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-15-f4bug@amsat.org>
2021-01-14target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé
gen_reserved_instruction() is easier to read than generate_exception_end(ctx, EXCP_RI), replace it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-12-f4bug@amsat.org>
2021-01-14target/mips: Replace gen_exception_err(err=0) by gen_exception_end()Philippe Mathieu-Daudé
generate_exception_err(err=0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-11-f4bug@amsat.org>
2021-01-14target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé
Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
2021-01-14target/mips/translate: Extract DisasContext structurePhilippe Mathieu-Daudé
Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207235539.4070364-2-f4bug@amsat.org>
2021-01-14target/mips: Rename translate_init.c as cpu-defs.cPhilippe Mathieu-Daudé
This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-10-f4bug@amsat.org>
2021-01-14target/mips: Move mmu_init() functions to tlb_helper.cPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
2021-01-14target/mips: Fix code style for checkpatch.plPhilippe Mathieu-Daudé
We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
2021-01-14target/mips: Rename helper.c as tlb_helper.cPhilippe Mathieu-Daudé
This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-13-f4bug@amsat.org>
2021-01-14target/mips: Move common helpers from helper.c to cpu.cPhilippe Mathieu-Daudé
The rest of helper.c is TLB related. Extract the non TLB specific functions to cpu.c, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-6-f4bug@amsat.org>
2021-01-14target/mips: Remove consecutive CONFIG_USER_ONLY ifdefsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-5-f4bug@amsat.org>
2021-01-14target/mips: Add !CONFIG_USER_ONLY comment after #endifPhilippe Mathieu-Daudé
To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-4-f4bug@amsat.org>
2021-01-14target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé
Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
2021-01-14target/mips: Inline cpu_state_reset() in mips_cpu_reset()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-2-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé
The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5Philippe Mathieu-Daudé
The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3Philippe Mathieu-Daudé
The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-14-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé
The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1Philippe Mathieu-Daudé
The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-12-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé
Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5Philippe Mathieu-Daudé
Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3Philippe Mathieu-Daudé
Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-9-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé
Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1Philippe Mathieu-Daudé
Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()Philippe Mathieu-Daudé
MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1Philippe Mathieu-Daudé
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Reorder CPU_MIPS5 definitionPhilippe Mathieu-Daudé
Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-3-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS commentPhilippe Mathieu-Daudé
Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-2-f4bug@amsat.org>
2021-01-14target/mips/addr: Add translation helpers for KSEG1Jiaxun Yang
It's useful for bootloader to do I/O operations. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-14target/mips: Replace CP0_Config0 magic values by proper definitionsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
2021-01-14target/mips: Add CP0 Config0 register definitions for MIPS3 ISAPhilippe Mathieu-Daudé
The MIPS3 and MIPS32/64 ISA use different definitions for the CP0 Config0 register. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
2021-01-12Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging * UI configury cleanups and Meson conversion * scripts/gdb improvements * WHPX cleanups and fixes * cirrus win32 CI improvements * meson gnutls workaround # gpg: Signature made Tue 12 Jan 2021 16:05:19 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: target/i386: Use X86Seg enum for segment registers configure: quote command line arguments in config.status configure: move Cocoa incompatibility checks to Meson configure: move GTK+ detection to Meson configure: move X11 detection to Meson gtk: remove CONFIG_GTK_GL cocoa: do not enable coreaudio automatically virtio-scsi: trace events meson: Propagate gnutls dependency Docs/RCU: Correct sample code of qatomic_rcu_set scripts/gdb: implement 'qemu bt' scripts/gdb: fix 'qemu coroutine' when users selects a non topmost stack frame meson: fix Cocoa option in summary whpx: move whpx_lapic_state from header to c file maintainers: Add me as Windows Hosted Continuous Integration maintainer cirrus/msys2: Cache msys2 mingw in a better way. cirrus/msys2: Exit powershell with $LastExitCode whpx: move internal definitions to whpx-internal.h whpx: rename whp-dispatch to whpx-internal.h meson: do not use CONFIG_VIRTFS Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: Don't decode insns in the XScale/iWMMXt space as cp insnsPeter Maydell
In commit cd8be50e58f63413c0 we converted the A32 coprocessor insns to decodetree. This accidentally broke XScale/iWMMXt insns, because it moved the handling of "cp insns which are handled by looking up the cp register in the hashtable" from after the call to the legacy disas_xscale_insn() decode to before it, with the result that all XScale/iWMMXt insns now UNDEF. Update valid_cp() so that it knows that on XScale cp 0 and 1 are not standard coprocessor instructions; this will cause the decodetree trans_ functions to ignore them, so that execution will correctly get through to the legacy decode again. Cc: qemu-stable@nongnu.org Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
2021-01-12target/i386: Use X86Seg enum for segment registersPhilippe Mathieu-Daudé
Use the dedicated X86Seg enum type for segment registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210109233427.749748-1-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-12whpx: move whpx_lapic_state from header to c fileYonggang Luo
This struct only used in whpx-apic.c, there is no need expose it in whpx.h. Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Message-Id: <20210107101919.80-6-luoyonggang@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-12whpx: move internal definitions to whpx-internal.hPaolo Bonzini
Only leave the external interface in sysemu/whpx.h. whpx_apic_in_platform is moved to a .c file because it needs whpx_state. Reported-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201219090637.1700900-3-pbonzini@redhat.com>
2021-01-12whpx: rename whp-dispatch to whpx-internal.hPaolo Bonzini
Rename the file in preparation for moving more implementation-internal definitions to it. The build is still broken though. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20201219090637.1700900-2-pbonzini@redhat.com>
2021-01-12target/arm: add aarch32 ID register fields to cpu.hLeif Lindholm
Add entries present in ARM DDI 0487F.c (August 2020). Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-7-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: add aarch64 ID register fields to cpu.hLeif Lindholm
Add entries present in ARM DDI 0487F.c (August 2020). Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-6-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.hLeif Lindholm
Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-5-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: make ARMCPU.ctr 64-bitLeif Lindholm
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the TminLine field in bits [37:32]. Extend the ctr field to be able to hold this context. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-4-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: make ARMCPU.clidr 64-bitLeif Lindholm
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-3-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: fix typo in cpu.h ID_AA64PFR1 field nameLeif Lindholm
SBSS -> SSBS Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20210108185154.8108-2-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: enable Small Translation tables in max CPURémi Denis-Courmont
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-12target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont
This adds for the Small Translation tables extension in AArch64 state. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-08target/arm: Remove timer_del()/timer_deinit() before timer_free()Peter Maydell
The Arm CPU finalize function uses a sequence of timer_del(), timer_deinit(), timer_free() to free the timer. The timer_deinit() step in this was always unnecessary, and now the timer_del() is implied by timer_free(), so we can collapse this down to simply calling timer_free(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201215154107.3255-5-peter.maydell@linaro.org
2021-01-08Remove superfluous timer_del() callsPeter Maydell
This commit is the result of running the timer-del-timer-free.cocci script on the whole source tree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Corey Minyard <cminyard@mvista.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201215154107.3255-4-peter.maydell@linaro.org
2021-01-08target/arm: Implement Cortex-M55 modelPeter Maydell
Now that we have implemented all the features needed by the v8.1M architecture, we can add the model of the Cortex-M55. This is the configuration without MVE support; we'll add MVE later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201210201433.26262-5-peter.maydell@linaro.org
2021-01-08target/arm: Implement FPCXT_NS fp system registerPeter Maydell
Implement the v8.1M FPCXT_NS floating-point system register. This is a little more complicated than FPCXT_S, because it has specific handling for "current FP state is inactive", and it only wants to do PreserveFPState(), not the full set of actions done by ExecuteFPCheck() which vfp_access_check() implements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201210201433.26262-4-peter.maydell@linaro.org
2021-01-08target/arm: Correct store of FPSCR value via FPCXT_SPeter Maydell
In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register, but we got the write behaviour wrong. On read, this register reads bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't just write back those bits -- it writes a value to the whole FPSCR, whose upper 4 bits are zeroes. We also incorrectly implemented the write-to-FPSCR as a simple store to vfp.xregs; this skips the "update the softfloat flags" part of the vfp_set_fpscr helper so the value would read back correctly but not actually take effect. Fix both of these things by doing a complete write to the FPSCR using the helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201210201433.26262-3-peter.maydell@linaro.org
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