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AgeCommit message (Expand)Author
2017-02-22target/ppc/POWER9: Direct all instr and data storage interrupts to the hypvSuraj Jitindar Singh
2017-02-22target/ppc/POWER9: Adapt LPCR handling for POWER9Suraj Jitindar Singh
2017-02-22target/ppc/POWER9: Add ISAv3.00 MMU definitionSuraj Jitindar Singh
2017-02-22target/ppc: Fix LPCR DPFD mask defineSuraj Jitindar Singh
2017-02-22target-ppc: Add xscvqpudz and xscvqpuwz instructionsBharata B Rao
2017-02-22target-ppc: Implement round to odd variants of quad FP instructionsBharata B Rao
2017-02-22target-ppc: add wait instructionNikunj A Dadhania
2017-02-22target-ppc: add slbsync implementationNikunj A Dadhania
2017-02-22target-ppc: add slbieg instructionNikunj A Dadhania
2017-02-22target-ppc: generate exception for copy/pasteNikunj A Dadhania
2017-02-22target-ppc: implement store atomic instructionBalamuruhan S
2017-02-22target-ppc: implement load atomic instructionBalamuruhan S
2017-02-22target-ppc: Add xsmaxjdp and xsminjdp instructionsBharata B Rao
2017-02-22target-ppc: Add xsmaxcdp and xsmincdp instructionsBharata B Rao
2017-02-22ppc: implement xssubqp instructionJose Ricardo Ziviani
2017-02-22ppc: implement xssqrtqp instructionJose Ricardo Ziviani
2017-02-22ppc: implement xsrqpxp instructionJose Ricardo Ziviani
2017-02-22ppc: implement xsrqpi[x] instructionJose Ricardo Ziviani
2017-02-16target-i386: correctly propagate retaddr into SVM helpersPaolo Bonzini
2017-02-16report guest crash information in GUEST_PANICKED eventAnton Nefedov
2017-02-16i386/cpu: add crash-information QOM propertyAnton Nefedov
2017-02-14Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into stagingPeter Maydell
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson
2017-02-14target/openrisc: Fix maddRichard Henderson
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Implement msyncRichard Henderson
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson
2017-02-14target/openrisc: Set flags on helpersRichard Henderson
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson
2017-02-13migration: consolidate VMStateField.startHalil Pasic
2017-02-10target-arm: Enable vPMU support under TCG modeWei Huang
2017-02-10target-arm: Add support for PMU register PMINTENSET_EL1Wei Huang
2017-02-10target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0Wei Huang
2017-02-10target-arm: Add support for PMU register PMSELR_EL0Wei Huang
2017-02-07target/arm: A32, T32: Create Instruction Syndromes for Data AbortsPeter Maydell
2017-02-07target/arm: Abstract out pbit/wbit tests in ARM ldr/str decodePeter Maydell
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