| Age | Commit message (Expand) | Author |
|---|
| 2018-03-02 | Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2018-03-0... | Peter Maydell |
| 2018-03-02 | target/arm: Enable ARM_FEATURE_V8_FCMA | Richard Henderson |
| 2018-03-02 | target/arm: Decode t32 simd 3reg and 2reg_scalar extension | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa32 armv8.3 2-reg-index | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa32 armv8.3 3-same | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa64 armv8.3 fcmla | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa64 armv8.3 fcadd | Richard Henderson |
| 2018-03-02 | target/arm: Add ARM_FEATURE_V8_FCMA | Richard Henderson |
| 2018-03-02 | target/arm: Enable ARM_FEATURE_V8_RDM | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa32 armv8.1 two reg and a scalar | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa32 armv8.1 three same | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa64 armv8.1 scalar/vector x indexed element | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa64 armv8.1 three same extra | Richard Henderson |
| 2018-03-02 | target/arm: Decode aa64 armv8.1 scalar three same extra | Richard Henderson |
| 2018-03-02 | target/arm: Refactor disas_simd_indexed size checks | Richard Henderson |
| 2018-03-02 | target/arm: Refactor disas_simd_indexed decode | Richard Henderson |
| 2018-03-02 | target/arm: Add ARM_FEATURE_V8_RDM | Richard Henderson |
| 2018-03-02 | target/arm: Add Cortex-M33 | Peter Maydell |
| 2018-03-02 | target/arm: Define init-svtor property for the reset secure VTOR value | Peter Maydell |
| 2018-03-02 | target/arm: Define an IDAU interface | Peter Maydell |
| 2018-03-02 | tricore: renamed masking of PIE | David Brenken |
| 2018-03-02 | tricore: renamed masking of IE | David Brenken |
| 2018-03-02 | tricore: added CORE_ID | David Brenken |
| 2018-03-02 | tricore: added some missing cpu instructions | David Brenken |
| 2018-03-01 | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180301-v2' into sta... | Peter Maydell |
| 2018-03-01 | s390x/tcg: fix loading 31bit PSWs with the highest bit set | David Hildenbrand |
| 2018-03-01 | target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU | Peter Maydell |
| 2018-03-01 | arm/translate-a64: add all single op FP16 to handle_fp_1src_half | Alex Bennée |
| 2018-03-01 | arm/translate-a64: implement simd_scalar_three_reg_same_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add all FP16 ops in simd_scalar_pairwise | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FMOV to simd_mod_imm | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/helper.c: re-factor rsqrte and add rsqrte_f16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FRECPE | Alex Bennée |
| 2018-03-01 | arm/helper.c: re-factor recpe and add recepe_f16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: initial decode for simd_two_reg_misc_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 x2 ops for simd_indexed | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 | Alex Bennée |
| 2018-03-01 | arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 | Alex Bennée |
