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2020-08-21target/xtensa: don't access BR regfile directlyMax Filippov
BR registers used in FPU comparison opcodes are available as opcode arguments for translators. Use them. This simplifies comparison helpers interface and makes them usable in FLIX bundles. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/xtensa: move FSR/FCR register accessorsMax Filippov
Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as they are FPU2000-specific. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/xtensa: rename FPU2000 translators and helpersMax Filippov
Add _s suffix to all FPU2000 opcode translators and helpers that also have double-precision variant to unify naming and allow adding DFPU implementations. Add _fpu2k_ to the names of helpers that will have different implementation for the DFPU . Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/xtensa: support copying registers up to 64 bits wideMax Filippov
FLIX dependency breaking code assumes that all registers are 32 bit wide. This may not always be correct. Extract actual register width from the associated register file and use it to create temporaries of correct width and generate correct data movement instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/xtensa: add geometry to xtensa_get_regfile_by_nameMax Filippov
Register file name may not uniquely identify a register file in the set of configurations. E.g. floating point registers may have different size in different configurations. Use register file geometry as additional identifier. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/xtensa: implement NMI supportMax Filippov
When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/xtensa: make opcode properties more dynamicMax Filippov
There's XtensaOpcodeOps::test_ill that is used to check whether opcode generates illegal opcode exception or not. The illegal opcode exception is not special and so this callback can be generalized to provide any XTENSA_OP_* flags that are not completely static. Introduce XtensaOpcodeOps::test_exceptions and convert all test_ill users to test_exceptions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21target/s390x: fix meson.build issuePaolo Bonzini
files() is needed to avoid ../meson.build:977:2: ERROR: File tcg-stub.c does not exist. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: link emulators without Makefile.targetPaolo Bonzini
The binaries move to the root directory, e.g. qemu-system-i386 or qemu-arm. This requires changes to qtests, CI, etc. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: targetPaolo Bonzini
Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: convert target/s390x/gen-features.hMarc-André Lureau
Needed by linux-user/s390x/cpu_loop.c; this removes the only use of HOST_CC. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: rename .inc.h files to .h.incPaolo Bonzini
Make it consistent with '.c.inc' and '.rst.inc'. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini
Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$(<D). In order to keep the include directives unchanged, the simplest solution is to generate headers with patterns like "trace/trace-audio.h" and place forwarding headers in the source tree such that for example "audio/trace.h" includes "trace/trace-audio.h". This patch is too ugly to be applied to the Makefiles now. It's only a way to separate the changes to the tracing header files from the Meson rewrite of the tracing logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-13target/ppc: Integrate icount to purr, vtb, and tbu40Gustavo Romero
Currently if option '-icount auto' is passed to the QEMU TCG to enable counting instructions the VM crashes with the following error report when Linux runs on it: qemu-system-ppc64: Bad icount read This happens because read/write access to the SPRs PURR, VTB, and TBU40 is not integrated to the icount framework. This commit fixes that issue by making the read/write access of these SPRs aware of icount framework, adding the proper gen_io_start() calls before calling the helpers to load/store these SPRs in TCG and ensuring that the associated TBs end immediately after, accordingly to what's in docs/devel/tcg-icount.rst. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Message-Id: <20200811153235.4527-1-gromero@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Fix SPE unavailable exception triggeringMatthieu Bucchianeri
When emulating certain floating point instructions or vector instructions on PowerPC machines, QEMU did not properly generate the SPE/Embedded Floating- Point Unavailable interrupt. See the buglink further below for references to the relevant NXP documentation. This patch fixes the behavior of some evfs* instructions that were incorrectly emitting the interrupt. More importantly, this patch fixes the behavior of several efd* and ev* instructions that were not generating the interrupt. Triggering the interrupt for these instructions fixes lazy FPU/vector context switching on some operating systems like Linux. Without this patch, the result of some double-precision arithmetic could be corrupted due to the lack of proper saving and restoring of the upper 32-bit part of the general-purpose registers. Buglink: https://bugs.launchpad.net/qemu/+bug/1888918 Buglink: https://bugs.launchpad.net/qemu/+bug/1611394 Signed-off-by: Matthieu Bucchianeri <matthieu.bucchianeri@leostella.com> Message-Id: <20200727175553.32276-1-matthieu.bucchianeri@leostella.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulh{su}d instructionsLijun Pan
vmulhsd: Vector Multiply High Signed Doubleword vmulhud: Vector Multiply High Unsigned Doubleword Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-5-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulh{su}w instructionsLijun Pan
vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-4-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add vmulld instructionLijun Pan
vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-6-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: convert vmuluwm to tcg_gen_gvec_mulLijun Pan
Convert the original implementation of vmuluwm to the more generic tcg_gen_gvec_mul. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-5-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: add byte-reverse br[dwh] instructionsLijun Pan
POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-4-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Enable Power ISA 3.1Lijun Pan
This patch enables the Power ISA 3.1 in QEMU. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-3-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Introduce Power ISA 3.1 flagLijun Pan
This flag will be used for Power10 instructions. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200701234344.91843-2-ljp@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-12target/ppc: Fix TCG leak with the evmwsmiaa instructionMatthieu Bucchianeri
Fix double-call to tcg_temp_new_i64(), where a temp is allocated both at declaration time and further down the implementation of gen_evmwsmiaa(). Note that gen_evmwsmia() and gen_evmwsmiaa() are still not implemented correctly, as they invoke gen_evmwsmi() which may return early, but the return is not propagated. This will be fixed in my patch for bug #1888918. Signed-off-by: Matthieu Bucchianeri <matthieu.bucchianeri@leostella.com> Message-Id: <20200727172114.31415-1-matthieu.bucchianeri@leostella.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-08-05target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64Peter Maydell
When a coprocessor instruction in an AArch32 guest traps to AArch32 Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields which are simply copies of the Rt and Rt2 fields from the trapped instruction. However, if the instruction is trapped from AArch32 to an AArch64 higher exception level, the Rt and Rt2 fields in the syndrome register (ESR_ELx) must be the AArch64 view of the register. This makes a difference if the AArch32 guest was in a mode other than User or System and it was using r13 or r14, or if it was in FIQ mode and using r8-r14. We don't know at translate time which AArch32 CPU mode we are in, so we leave the values we generate in our prototype syndrome register value at translate time as the raw Rt/Rt2 from the instruction, and instead correct them to the AArch64 view when we find we need to take an exception from AArch32 to AArch64 with one of these syndrome values. Fixes: https://bugs.launchpad.net/qemu/+bug/1879587 Reported-by: Julien Freche <julien@bedrocksystems.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200804193903.31240-1-peter.maydell@linaro.org
2020-08-05target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth
The code currently fails to compile on 32-bit big endian hosts: target/riscv/vector_helper.c: In function 'vext_clear': target/riscv/vector_helper.c:154:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); ^ target/riscv/vector_helper.c:155:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); ^ cc1: all warnings being treated as errors We should not use "long long" (i.e. 64-bit) values here to avoid the problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead. Fixes: 751538d5da ("add vector stride load and store instructions") Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200804170055.2851-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-04target/arm: Fix decode of LDRA[AB] instructionsPeter Collingbourne
These instructions use zero as the discriminator, not SP. Signed-off-by: Peter Collingbourne <pcc@google.com> Message-id: 20200804002849.30268-1-pcc@google.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03target/arm: Avoid maybe-uninitialized warning with gcc 4.9Kaige Li
GCC version 4.9.4 isn't clever enough to figure out that all execution paths in disas_ldst() that use 'fn' will have initialized it first, and so it warns: /home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’: /home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized] fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), ^ /home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here AtomicThreeOpFn *fn; ^ Make it happy by initializing the variable to NULL. Signed-off-by: Kaige Li <likaige@loongson.cn> Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Clean up commit message and note which gcc version this was] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03target/arm: Fix AddPAC error indicationRichard Henderson
The definition of top_bit used in this function is one higher than that used in the Arm ARM psuedo-code, which put the error indication at top_bit - 1 at the wrong place, which meant that it wasn't visible to Auth. Fixing the definition of top_bit requires more changes, because its most common use is for the count of bits in top_bit:bot_bit, which would then need to be computed as top_bit - bot_bit + 1. For now, prefer the minimal fix to the error indication alone. Fixes: 63ff0ca94cb Reported-by: Derrick McKee <derrick.mckee@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200728195706.11087-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added comment about the divergence from the pseudocode] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-28Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200727' into staging target-arm queue: * ACPI: Assert that we don't run out of the preallocated memory * hw/misc/aspeed_sdmc: Fix incorrect memory size * target/arm: Always pass cacheattr in S1_ptw_translate * docs/system/arm/virt: Document 'mte' machine option * hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot * target/arm: Improve IMPDEF algorithm for IRG # gpg: Signature made Mon 27 Jul 2020 16:18:38 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200727: target/arm: Improve IMPDEF algorithm for IRG hw/arm/boot: Fix MTE for EL3 direct kernel boot hw/arm/boot: Fix PAUTH for EL3 direct kernel boot docs/system/arm/virt: Document 'mte' machine option target/arm: Always pass cacheattr in S1_ptw_translate hw/misc/aspeed_sdmc: Fix incorrect memory size ACPI: Assert that we don't run out of the preallocated memory Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27target/arm: Improve IMPDEF algorithm for IRGRichard Henderson
When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF, and the kernel is not expected to have set RGSR_EL1. Force a non-zero value into SEED, so that we do not continually return the same tag. Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200724163853.504655-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27target/arm: Always pass cacheattr in S1_ptw_translateRichard Henderson
When we changed the interface of get_phys_addr_lpae to require the cacheattr parameter, this spot was missed. The compiler is unable to detect the use of NULL vs the nonnull attribute here. Fixes: 7e98e21c098 Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Jan Kiszka <jan.kiskza@siemens.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-fixes-for-rc2-270720-1' into staging Various fixes for rc2: - get shippable working again - semihosting bug fixes - tweak tb-size handling for low memory machines - i386 compound literal float fix - linux-user MAP_FIXED->MAP_NOREPLACE on fallback - docker binfmt_misc fixes - linux-user nanosleep fix - tests/vm drain console fixes # gpg: Signature made Mon 27 Jul 2020 09:45:31 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-fixes-for-rc2-270720-1: tests/vm: add shutdown timeout in basevm.py python/qemu: Change ConsoleSocket to optionally drain socket. python/qemu: Cleanup changes to ConsoleSocket linux-user, ppc: fix clock_nanosleep() for linux-user-ppc linux-user: fix clock_nanosleep() tests/docker: add support for DEB_KEYRING tests/docker: fix binfmt_misc image building tests/docker: fix update command due to python3 str/bytes distinction linux-user: don't use MAP_FIXED in pgd_find_hole_fallback target/i386: floatx80: avoid compound literals in static initializers accel/tcg: better handle memory constrained systems util/oslib-win32: add qemu_get_host_physmem implementation util: add qemu_get_host_physmem utility function semihosting: don't send the trailing '\0' semihosting: defer connect_chardevs a little more to use serialx shippable: add one more qemu to registry url Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27target/i386: floatx80: avoid compound literals in static initializersLaszlo Ersek
Quoting ISO C99 6.7.8p4, "All the expressions in an initializer for an object that has static storage duration shall be constant expressions or string literals". The compound literal produced by the make_floatx80() macro is not such a constant expression, per 6.6p7-9. (An implementation may accept it, according to 6.6p10, but is not required to.) Therefore using "floatx80_zero" and make_floatx80() for initializing "f2xm1_table" and "fpatan_table" is not portable. And gcc-4.8 in RHEL-7.6 actually chokes on them: > target/i386/fpu_helper.c:871:5: error: initializer element is not constant > { make_floatx80(0xbfff, 0x8000000000000000ULL), > ^ We've had the make_floatx80_init() macro for this purpose since commit 3bf7e40ab914 ("softfloat: fix for C99", 2012-03-17), so let's use that macro again. Fixes: eca30647fc0 ("target/i386: reimplement f2xm1 using floatx80 operations") Fixes: ff57bb7b632 ("target/i386: reimplement fpatan using floatx80 operations") Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Joseph Myers <joseph@codesourcery.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Link: https://lists.gnu.org/archive/html/qemu-devel/2017-08/msg06566.html Link: https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg04714.html Message-Id: <20200716144251.23004-1-lersek@redhat.com> Message-Id: <20200724064509.331-8-alex.bennee@linaro.org>
2020-07-27pseries: fix kvmppc_set_fwnmi()Laurent Vivier
QEMU issues the ioctl(KVM_CAP_PPC_FWNMI) on the first vCPU. If the first vCPU is currently running, the vCPU mutex is held and the ioctl() cannot be done and waits until the mutex is released. This never happens and the VM is stuck. To avoid this deadlock, issue the ioctl on the same vCPU doing the RTAS call. The problem can be reproduced by booting a guest with several vCPUs (the probability to have the problem is (n - 1) / n, n = # of CPUs), and then by triggering a kernel crash with "echo c >/proc/sysrq-trigger". On the reboot, the kernel hangs after: ... [ 0.000000] ----------------------------------------------------- [ 0.000000] ppc64_pft_size = 0x0 [ 0.000000] phys_mem_size = 0x48000000 [ 0.000000] dcache_bsize = 0x80 [ 0.000000] icache_bsize = 0x80 [ 0.000000] cpu_features = 0x0001c06f8f4f91a7 [ 0.000000] possible = 0x0003fbffcf5fb1a7 [ 0.000000] always = 0x00000003800081a1 [ 0.000000] cpu_user_features = 0xdc0065c2 0xaee00000 [ 0.000000] mmu_features = 0x3c006041 [ 0.000000] firmware_features = 0x00000085455a445f [ 0.000000] physical_start = 0x8000000 [ 0.000000] ----------------------------------------------------- [ 0.000000] numa: NODE_DATA [mem 0x47f33c80-0x47f3ffff] Fixes: ec010c00665b ("ppc/spapr: KVM FWNMI should not be enabled until guest requests it") Cc: npiggin@gmail.com Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20200724083533.281700-1-lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-07-26Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200725' into stagingPeter Maydell
Fix some cputlb commentary Fix an hppa temporary leak Fix an i386 translation issue with loop insns # gpg: Signature made Sat 25 Jul 2020 17:03:59 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20200725: target/i386: Save cc_op before loop insns target/hppa: Free some temps in do_sub tcg: update comments for save_iotlb_data in cputlb Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-24target/i386: Save cc_op before loop insnsRichard Henderson
We forgot to update cc_op before these branch insns, which lead to losing track of the current eflags. Buglink: https://bugs.launchpad.net/qemu/+bug/1888165 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200720154028.477457-1-richard.henderson@linaro.org>
2020-07-24target/hppa: Free some temps in do_subRichard Henderson
Two temps allocated but not freed. Do enough subtractions within a single TB and one can run out of temps entirely. Fixes: b2167459ae ("target-hppa: Implement basic arithmetic") Buglink: https://bugs.launchpad.net/qemu/+bug/1880287 Tested-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200720174039.517902-1-richard.henderson@linaro.org>
2020-07-24Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-24' ↵Peter Maydell
into staging Error reporting patches patches for 2020-07-24 # gpg: Signature made Fri 24 Jul 2020 14:03:44 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2020-07-24: qapi/error: Check format string argument in error_*prepend() sd/milkymist-memcard: Fix format string error: Strip trailing '\n' from error string arguments (again) coccinelle/err-bad-newline: Fix for Python 3, and add patterns Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-24error: Strip trailing '\n' from error string arguments (again)Markus Armbruster
Tracked down with scripts/coccinelle/err-bad-newline.cocci. Cc: Peter Xu <peterx@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200722084048.1726105-3-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Xu <peterx@redhat.com>
2020-07-24Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-next-for-5.1-pull-request' into staging x86 bug fix for -rc2 A fix from Vitaly Kuznetsov for a CPU reset bug reported by Jan Kiszka. # gpg: Signature made Thu 23 Jul 2020 20:10:40 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-for-5.1-pull-request: KVM: fix CPU reset wrt HF2_GIF_MASK Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-23KVM: fix CPU reset wrt HF2_GIF_MASKVitaly Kuznetsov
HF2_GIF_MASK is set in env->hflags2 unconditionally on CPU reset (see x86_cpu_reset()) but when calling KVM_SET_NESTED_STATE, KVM_STATE_NESTED_GIF_SET is only valid for nSVM as e.g. nVMX code looks like if (kvm_state->hdr.vmx.vmxon_pa == -1ull) { if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS) return -EINVAL; } Also, when adjusting the environment after KVM_GET_NESTED_STATE we need not reset HF2_GIF_MASK on VMX as e.g. x86_cpu_pending_interrupt() expects it to be set. Alternatively, we could've made env->hflags2 SVM-only. Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Fixes: b16c0e20c742 ("KVM: add support for AMD nested live migration") Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200723142701.2521161-1-vkuznets@redhat.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-22target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li
The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-Id: <eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-22target/riscv: fix vector index load/store constraintsLIU Zhiwei
Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-22target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-1-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-20hw/arm/virt: Enable MTE via a machine propertyRichard Henderson
Control this cpu feature via a machine property, much as we do with secure=on, since both require specialized support in the machine setup to be functional. Default MTE to off, since this feature implies extra overhead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200713213341.590275-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-16i386: hvf: Explicitly set CR4 guest/host maskRoman Bolshakov
Removal of register reset omitted initialization of CR4 guest/host mask. x86_64 guests aren't booting without it. Fixes: 5009ef22c6bb2 ("i386: hvf: Don't duplicate register reset") Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200714090726.41082-1-r.bolshakov@yadro.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16target/i386: add the missing vmx features for Skylake-Server and ↵Chenyi Qiang
Cascadelake-Server CPU models Add the missing vmx features in Skylake-Server and Cascadelake-Server CPU models based on the output of Paolo's script. Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20200714084148.26690-4-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16target/i386: fix model number and add missing features for Icelake-Server ↵Chenyi Qiang
CPU model Add the missing features(sha_ni, avx512ifma, rdpid, fsrm, vmx-rdseed-exit, vmx-pml, vmx-eptp-switching) and change the model number to 106 in the Icelake-Server-v4 CPU model. Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20200714084148.26690-3-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16target/i386: add fast short REP MOV supportChenyi Qiang
For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g Icelake and Tigerlake, expose it to the guest VM. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20200714084148.26690-2-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 13:50:17 +0000