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2018-01-31target/hppa: Implement PROBE for system modeRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Fix 32-bit operand masks for 0E FCVTRichard Henderson
We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Enable MTTCGRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement STWARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement a pause instructionRichard Henderson
This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement LDSID for system modeHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Fix commentHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Increase number of temp regsRichard Henderson
HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Only use EXCP_DTLB_MISSRichard Henderson
Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement B,GATE insnRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Add migration for the cpuRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Add system registers to gdbstubRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Optimize for flat addressing spaceRichard Henderson
Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement halt and reset instructionsHelge Deller
Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement SYNCDMA insnRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LCIRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LPARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LDWARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement P*TLB and P*TLBE insnsRichard Henderson
We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement I*TLBA and I*TLBP insnsRichard Henderson
The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Log unimplemented instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement the interval timerRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement external interruptsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement tlb_fillRichard Henderson
However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement IASQRichard Henderson
Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Avoid privilege level decrease during branchesRichard Henderson
These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Use space registers in data operationsRichard Henderson
This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement unaligned access trapRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interruptRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement rfiRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Adjust insn mask for mfctl,wRichard Henderson
While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Add control registersRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Add space registersRichard Henderson
Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement the system mask instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement mmu_idx from IA privilege levelRichard Henderson
Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Split address size from register sizeRichard Henderson
For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Define hardware exception typesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Disable gateway page emulation for system modeRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Define the rest of the PSWRichard Henderson
We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Skeleton support for hppa-softmmuHelge Deller
With the addition of default-configs/hppa-softmmu.mak, this will compile. It is not enabled with this patch, however. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-29target/ppc/kvm: Add cap_ppc_safe_[cache/bounds_check/indirect_branch]Suraj Jitindar Singh
Add three new kvm capabilities used to represent the level of host support for three corresponding workarounds. Host support for each of the capabilities is queried through the new ioctl KVM_PPC_GET_CPU_CHAR which returns four uint64 quantities. The first two, character and behaviour, represent the available characteristics of the cpu and the behaviour of the cpu respectively. The second two, c_mask and b_mask, represent the mask of known bits for the character and beheviour dwords respectively. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Correct some compile errors due to name change in final kernel patch version] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-01-26Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Thu 25 Jan 2018 15:15:03 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: add HMP command "info tlb" target/m68k: add pflush/ptest target/m68k: add moves target/m68k: add index parameter to gen_load()/gen_store() and Co. target/m68k: add Transparent Translation target/m68k: add MC68040 MMU accel/tcg: add size paremeter in tlb_fill() target/m68k: fix TCG variable double free Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-25target/m68k: add HMP command "info tlb"Laurent Vivier
Dump MMU state and address mappings. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-8-laurent@vivier.eu>
2018-01-25target/m68k: add pflush/ptestLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-7-laurent@vivier.eu>
2018-01-25target/m68k: add movesLaurent Vivier
and introduce SFC and DFC control registers. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-6-laurent@vivier.eu>
2018-01-25target/m68k: add index parameter to gen_load()/gen_store() and Co.Laurent Vivier
The instruction "moves" can select source and destination address space (user or kernel). This patch modifies all the load/store functions to be able to provide the address space the caller wants to use instead of using the current one. All the callers are modified to provide the default address space to these functions. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-5-laurent@vivier.eu>
2018-01-25target/m68k: add Transparent TranslationLaurent Vivier
Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-4-laurent@vivier.eu>
2018-01-25target/m68k: add MC68040 MMULaurent Vivier
Only add MC68040 MMU page table processing and related registers (Special Status Word, Translation Control Register, User Root Pointer and Supervisor Root Pointer). Transparent Translation Registers, DFC/SFC and pflush/ptest will be added later. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-3-laurent@vivier.eu>
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
2018-01-25target/m68k: fix TCG variable double freeLaurent Vivier
t64 is also unconditionally freed after the switch () { ... } Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180119114444.7590-1-laurent@vivier.eu>
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