slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-09-27	target/riscv: Set the CPU resetvec directly	Alistair Francis
2022-09-27	target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml	Andrew Burgess
2022-09-27	target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}	Weiwei Li
2022-09-27	target/riscv: Remove sideleg and sedeleg	Rahul Pathak
2022-09-26	Merge tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydel...	Stefan Hajnoczi
2022-09-22	Merge tag 'pull-hex-20220919' of https://github.com/quic/qemu into staging	Stefan Hajnoczi
2022-09-22	target/arm: Add is_secure parameter to get_phys_addr_pmsav5	Richard Henderson
2022-09-22	target/arm: Add secure parameter to get_phys_addr_pmsav7	Richard Henderson
2022-09-22	target/arm: Add is_secure parameter to pmsav7_use_background_region	Richard Henderson
2022-09-22	target/arm: Add secure parameter to get_phys_addr_pmsav8	Richard Henderson
2022-09-22	target/arm: Add is_secure parameter to get_phys_addr_v6	Richard Henderson
2022-09-22	target/arm: Add is_secure parameter to get_phys_addr_v5	Richard Henderson
2022-09-22	target/arm: Add secure parameter to pmsav8_mpu_lookup	Richard Henderson
2022-09-22	target/arm: Add is_secure parameter to v8m_security_lookup	Richard Henderson
2022-09-22	target/arm: Remove is_subpage argument to pmsav8_mpu_lookup	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in get_phys_addr_v5	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in get_phys_addr_v6	Richard Henderson
2022-09-22	target/arm: Use GetPhysAddrResult in get_phys_addr_lpae	Richard Henderson
2022-09-22	target/arm: Create GetPhysAddrResult	Richard Henderson
2022-09-22	target/arm: Fix alignment for VLD4.32	Clément Chigot
2022-09-21	Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ...	Stefan Hajnoczi
2022-09-21	Merge tag 'pull-ppc-20220920' of https://gitlab.com/danielhb/qemu into staging	Stefan Hajnoczi
2022-09-21	target/m68k: always call gen_exit_tb() after writes to SR	Mark Cave-Ayland
2022-09-21	target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K	Mark Cave-Ayland
2022-09-21	target/m68k: Perform writback before modifying SR	Richard Henderson
2022-09-21	target/m68k: Fix MACSR to CCR	Richard Henderson
2022-09-21	target/m68k: Implement atomic test-and-set	Richard Henderson
2022-09-20	target/ppc: Clear fpstatus flags on helpers missing it	Víctor Colombo
2022-09-20	target/ppc: Zero second doubleword of VSR registers for FPR insns	Víctor Colombo
2022-09-20	target/ppc: Set OV32 when OV is set	Víctor Colombo
2022-09-20	target/ppc: Zero second doubleword for VSX madd instructions	Víctor Colombo
2022-09-20	target/ppc: Set result to QNaN for DENBCD when VXCVI occurs	Víctor Colombo
2022-09-20	target/ppc: Zero second doubleword in DFP instructions	Víctor Colombo
2022-09-20	target/ppc: Remove unused xer_* macros	Víctor Colombo
2022-09-20	target/ppc: Remove extra space from s128 field in ppc_vsr_t	Víctor Colombo
2022-09-20	target/ppc: Merge fsqrt and fsqrts helpers	Víctor Colombo
2022-09-20	target/ppc: Move fsqrts to decodetree	Víctor Colombo
2022-09-20	target/ppc: Move fsqrt to decodetree	Víctor Colombo
2022-09-20	target/ppc: Implement hashstp and hashchkp	Víctor Colombo
2022-09-20	target/ppc: Implement hashst and hashchk	Víctor Colombo
2022-09-20	target/ppc: Add HASHKEYR and HASHPKEYR SPRs	Víctor Colombo
2022-09-19	Hexagon (target/hexagon) remove unused encodings	Taylor Simpson
2022-09-19	target/i386: introduce insn_get_addr	Paolo Bonzini
2022-09-19	target/i386: REPZ and REPNZ are mutually exclusive	Paolo Bonzini
2022-09-19	target/i386: fix INSERTQ implementation	Paolo Bonzini
2022-09-19	target/i386: correctly mask SSE4a bit indices in register operands	Paolo Bonzini