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2020-05-14target/arm: Tidy handle_vec_simd_shriRichard Henderson
Now that we've converted all cases to gvec, there is quite a bit of dead code at the end of the function. Remove it. Sink the call to gen_gvec_fn2i to the end, loading a function pointer within the switch statement. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200513163245.17915-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14target/arm: Remove unnecessary range check for VSHLRichard Henderson
In 1dc8425e551, while converting to gvec, I added an extra range check against the shift count. This was unnecessary because the encoding of the shift count produces 0 to the element size - 1. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200513163245.17915-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14target/arm: Create gen_gvec_{sri,sli}Richard Henderson
The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed. When we reuse this for SVE, tcg-gvec-op may decide to use an out-of-line helper due to longer vector lengths. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200513163245.17915-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14target/arm: Create gen_gvec_{u,s}{rshr,rsra}Richard Henderson
Create vectorized versions of handle_shri_with_rndacc for shift+round and shift+round+accumulate. Add out-of-line helpers in preparation for longer vector lengths from SVE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200513163245.17915-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14target/arm: Create gen_gvec_[us]sraRichard Henderson
The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed. When we reuse this for SVE, tcg-gvec-op may decide to use an out-of-line helper due to longer vector lengths. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200513163245.17915-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-14target/arm: Use correct GDB XML for M-profile coresPeter Maydell
GDB's remote protocol requires M-profile cores to use the feature name 'org.gnu.gdb.arm.m-profile' instead of the 'org.gnu.gdb.arm.core' feature used for A- and R-profile cores. We weren't doing this, which meant GDB treated our M-profile cores like A-profile ones. This mostly doesn't matter, but for instance means that it doesn't correctly handle backtraces where an M-profile exception frame is involved. Ship a copy of GDB's arm-m-profile.xml and use it on the M-profile cores. The integer registers have the same offsets as the arm-core.xml, but register 25 is the M-profile XPSR rather than the A-profile CPSR, so we need to update arm_cpu_gdb_read_register() and arm_cpu_gdb_write_register() to handle XSPR reads and writes. Fixes: https://bugs.launchpad.net/qemu/+bug/1877136 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200507134755.13997-1-peter.maydell@linaro.org
2020-05-14target/microblaze: monitor: Increase the number of registers reportedJoe Komlodi
Increase the number of registers reported to match GDB. Registers that aren't modeled are reported as 0. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589393329-223076-4-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14target/microblaze: gdb: Fix incorrect SReg reportingJoe Komlodi
SRegs used to be reported to GDB by iterating over the SRegs array, however we do not store them in an order that allows them to be reported to GDB in that way. To fix this, a simple map is used to map the register GDB wants to its location in the SRegs array. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589393329-223076-3-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14target/microblaze: gdb: Extend the number of registers presented to GDBJoe Komlodi
Increase the number of Microblaze registers QEMU will report when talking to GDB. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589393329-223076-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14target/microblaze: Fix FPU2 instruction checkJoe Komlodi
The check to see if we can use FPU2 instructions would return 0 if cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK. This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589219346-106769-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-14target/microblaze: Add MFS Rd,EDR translationTong Ho
This is to fix cpu-abort with 'qemu: fatal: unknown mfs reg d' (in the default case) when microblaze guest issues 'MFS Rd,EDR' instruction. Since embeddedsw release 2019.2, XPlm_ExceptionHandler() issues the instruction on exception, and microblaze model aborts when PLM firmware guest encounters an exception. Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-Id: <20200512143649.21655-2-edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2020-05-11target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)Richard Henderson
DUP (indexed) can duplicate 128-bit elements, so using esz unconditionally can assert in tcg_gen_gvec_dup_imm. Fixes: 8711e71f9cbb Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20200507172352.15418-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLARichard Henderson
Now that we can pass 7 parameters, do not encode register operands within simd_data. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200507172352.15418-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Restrict TCG cpus to TCG accelPhilippe Mathieu-Daudé
A KVM-only build won't be able to run TCG cpus. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-6-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUsPhilippe Mathieu-Daudé
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200504172448.9402-5-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]Philippe Mathieu-Daudé
Use ARRAY_SIZE() to iterate over ARMCPUInfo[]. Since on the aarch64-linux-user build, arm_cpus[] is empty, add the cpu_count variable and only iterate when it is non-zero. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-4-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Make set_feature() available for other filesThomas Huth
Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to cpu.h. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-3-philmd@redhat.com Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature, cpu_register] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm/kvm: Inline set_feature() callsPhilippe Mathieu-Daudé
We want to move the inlined declarations of set_feature() from cpu*.c to cpu.h. To avoid clashing with the KVM declarations, inline the few KVM calls. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200504172448.9402-2-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Remove sve_memopidxRichard Henderson
None of the sve helpers use TCGMemOpIdx any longer, so we can stop passing it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Reuse sve_probe_page for gather loadsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Reuse sve_probe_page for scatter storesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Reuse sve_probe_page for gather first-fault loadsRichard Henderson
This avoids the need for a separate set of helpers to implement no-fault semantics, and will enable MTE in the future. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use SVEContLdSt for contiguous storesRichard Henderson
Follow the model set up for contiguous loads. This handles watchpoints correctly for contiguous stores, recognizing the exception before any changes to memory. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Update contiguous first-fault and no-fault loadsRichard Henderson
With sve_cont_ldst_pages, the differences between first-fault and no-fault are minimal, so unify the routines. With cpu_probe_watchpoint, we are able to make progress through pages with TLB_WATCHPOINT set when the watchpoint does not actually fire. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use SVEContLdSt for multi-register contiguous loadsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Handle watchpoints in sve_ld1_rRichard Henderson
Handle all of the watchpoints for active elements all at once, before we've modified the vector register. This removes the TLB_WATCHPOINT bit from page[].flags, which means that we can use the normal fast path via RAM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use SVEContLdSt in sve_ld1_rRichard Henderson
First use of the new helper functions, so we can remove the unused markup. No longer need a scratch for user-only, as we completely probe the page set before reading; system mode still requires a scratch for MMIO. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Adjust interface of sve_ld1_host_fnRichard Henderson
The current interface includes a loop; change it to load a single element. We will then be able to use the function for ld{2,3,4} where individual vector elements are not adjacent. Replace each call with the simplest possible loop over active elements. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Add sve infrastructure for page lookupRichard Henderson
For contiguous predicated memory operations, we want to minimize the number of tlb lookups performed. We have open-coded this for sve_ld1_r, but for correctness with MTE we will need this for all of the memory operations. Create a structure that holds the bounds of active elements, and metadata for two pages. Add routines to find those active elements, lookup the pages, and run watchpoints for those pages. Temporarily mark the functions unused to avoid Werror. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Drop manual handling of set/clear_helper_retaddrRichard Henderson
Since we converted back to cpu_*_data_ra, we do not need to do this ourselves. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fnRichard Henderson
Use the "normal" memory access functions, rather than the softmmu internal helper functions directly. Since fb901c905dc3, cpu_mem_index is now a simple extract from env->hflags and not a large computation. Which means that it's now more work to pass around this value than it is to recompute it. This only adjusts the primitives, and does not clean up all of the uses within sve_helper.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200508154359.7494-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-11target/arm: Drop access_el3_aa32ns_aa64any()Edgar E. Iglesias
Calling access_el3_aa32ns() works for AArch32 only cores but it does not handle 32-bit EL2 on top of 64-bit EL3 for mixed 32/64-bit cores. Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns() and only use the latter. Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2") Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20200505141729.31930-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-07Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200507' ↵Peter Maydell
into staging ppc patch queue for 2020-04-07 First pull request for qemu-5.1. This includes: * Removal of all remaining cases where we had CAS triggered reboots * A number of improvements to NMI injection * Support for partition scoped radix translation in softmmu * Some fixes for NVDIMM handling * A handful of other minor fixes # gpg: Signature made Thu 07 May 2020 06:00:55 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.1-20200507: target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9 spapr_nvdimm: Tweak error messages spapr_nvdimm.c: make 'label-size' mandatory target/ppc: Add support for Radix partition-scoped translation target/ppc: Rework ppc_radix64_walk_tree() for partition-scoped translation target/ppc: Extend ppc_radix64_check_prot() with a 'partition_scoped' bool target/ppc: Introduce ppc_radix64_xlate() for Radix tree translation spapr: Don't allow unplug of NVLink2 devices target/ppc: Assert if HV mode is set when running under a pseries machine target/ppc: Introduce a relocation bool in ppc_radix64_handle_mmu_fault() target/ppc: Enforce that the root page directory size must be at least 5 spapr: Drop CAS reboot flag spapr/cas: Separate CAS handling from rebuilding the FDT spapr: Simplify selection of radix/hash during CAS ppc/pnv: Add support for NMI interface ppc/spapr: tweak change system reset helper spapr: Don't check capabilities removed between CAS calls target/ppc: Improve syscall exception logging Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-05-07target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9Daniele Buono
Starting with Clang v9, -Wtype-limits is implemented and triggers a few "result of comparison is always true" errors when compiling PPC32 targets. The comparisons seem to be necessary only on PPC64, since the else branch in PPC32 only has a "g_assert_not_reached();" in all cases. This patch restructures the code so that the actual if/else is done on a local flag variable, that is set accordingly for PPC64, and always true for PPC32. Signed-off-by: Daniele Buono <dbuono@linux.vnet.ibm.com> Message-Id: <20200505183818.32688-2-dbuono@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Add support for Radix partition-scoped translationCédric Le Goater
The Radix tree translation model currently supports process-scoped translation for the PowerNV machine (Hypervisor mode) and for the pSeries machine (Guest mode). Guests running under an emulated Hypervisor (PowerNV machine) require a new type of Radix translation, called partition-scoped, which is missing today. The Radix tree translation is a 2 steps process. The first step, process-scoped translation, converts an effective Address to a guest real address, and the second step, partition-scoped translation, converts a guest real address to a host real address. There are difference cases to covers : * Hypervisor real mode access: no Radix translation. * Hypervisor or host application access (quadrant 0 and 3) with relocation on: process-scoped translation. * Guest OS real mode access: only partition-scoped translation. * Guest OS real or guest application access (quadrant 0 and 3) with relocation on: both process-scoped translation and partition-scoped translations. * Hypervisor access in quadrant 1 and 2 with relocation on: both process-scoped translation and partition-scoped translations. The radix tree partition-scoped translation is performed using tables pointed to by the first double-word of the Partition Table Entries and process-scoped translation uses tables pointed to by the Process Table Entries (second double-word of the Partition Table Entries). Both partition-scoped and process-scoped translations process are identical and thus the radix tree traversing code is largely reused. However, errors in partition-scoped translations generate hypervisor exceptions. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200403140056.59465-5-clg@kaod.org> [dwg: Fixup from Greg Kurz folded in] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Rework ppc_radix64_walk_tree() for partition-scoped translationCédric Le Goater
The ppc_radix64_walk_tree() routine walks through the nested radix tables to look for a PTE. Split it in two and introduce a new routine ppc_radix64_next_level() which we will use for partition-scoped Radix translation when translating the process tree addresses. The prototypes are slightly change to use a 'AddressSpace *' parameter, instead of a 'PowerPCCPU *' which is not required, and to return an error code instead of a PTE value. It clarifies error handling in the callers. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200403140056.59465-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Extend ppc_radix64_check_prot() with a 'partition_scoped' boolCédric Le Goater
This prepares ground for partition-scoped Radix translation. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20200403140056.59465-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Introduce ppc_radix64_xlate() for Radix tree translationCédric Le Goater
This is moving code under a new ppc_radix64_xlate() routine shared by the MMU Radix page fault handler and the 'get_phys_page_debug' PPC callback. The difference being that 'get_phys_page_debug' does not generate exceptions. The specific part of process-scoped Radix translation is moved under ppc_radix64_process_scoped_xlate() in preparation of the future support for partition-scoped Radix translation. Routines raising the exceptions now take a 'cause_excp' bool to cover the 'get_phys_page_debug' case. It should be functionally equivalent. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200403140056.59465-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Assert if HV mode is set when running under a pseries machineCédric Le Goater
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200330094946.24678-4-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Introduce a relocation bool in ppc_radix64_handle_mmu_fault()Cédric Le Goater
It will ease the introduction of new routines for partition-scoped Radix translation. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200330094946.24678-3-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Enforce that the root page directory size must be at least 5Suraj Jitindar Singh
According to the ISA the root page directory size of a radix tree for either process- or partition-scoped translation must be >= 5. Thus add this to the list of conditions checked when validating the partition table entry in validate_pate(); Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200330094946.24678-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07ppc/spapr: tweak change system reset helperNicholas Piggin
Rather than have the helper take an optional vector address override, instead have its caller modify env->nip itself. This is more consistent when adding pnv nmi support, and also with mce injection added later. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20200325144147.221875-2-npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-07target/ppc: Improve syscall exception loggingNicholas Piggin
system calls (at least in Linux) use registers r3-r8 for inputs, so include those registers in the dump. This also adds a mode for PAPR hcalls, which have a different calling convention. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20200317054918.199161-1-npiggin@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-05-06target/arm: Use tcg_gen_gvec_dup_immRichard Henderson
In a few cases, we're able to remove some manual replication. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-05-06target/ppc: Use tcg_gen_gvec_dup_immRichard Henderson
We can now unify the implementation of the 3 VSPLTI instructions. Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-05-06target/s390x: Use tcg_gen_gvec_dup_immRichard Henderson
The gen_gvec_dupi switch is unnecessary with the new function. Replace it with a local gen_gvec_dup_imm that takes care of the register to offset conversion and length arguments. Drop zero_vec and use use gen_gvec_dup_imm with 0. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-05-06target/m68k: fix gdb for m68xxxKONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects a coldfire FPU instead of the default m68881 FPU. This is not OK because the m68881 floats registers are 96 bits wide so it crashes GDB with the following error message: (gdb) target remote localhost:7960 Remote debugging using localhost:7960 warning: Register "fp0" has an unsupported size (96 bits) warning: Register "fp1" has an unsupported size (96 bits) ... Remote 'g' packet reply is too long (expected 148 bytes, got 180 bytes): \ 00000000000[...]0000 With this patch: qemu-system-m68k -M none -cpu m68020 -s -S (gdb) tar rem :1234 Remote debugging using :1234 warning: No executable has been specified and target does not support determining executable automatically. Try using the "file" command. 0x00000000 in ?? () (gdb) p $fp0 $1 = nan(0xffffffffffffffff) Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1588094279-17913-3-git-send-email-frederic.konrad@adacore.com> Message-Id: <20200430190122.4592-10-alex.bennee@linaro.org>
2020-05-06gdbstub: Introduce gdb_get_float64() to get 64-bit float registersPhilippe Mathieu-Daudé
When converted to use GByteArray in commits 462474d760c and a010bdbe719, the call to stfq_p() was removed. This call serialize a float. Since we now use a GByteArray, we can not use stfq_p() directly. Introduce the gdb_get_float64() helper to load a float64 register. Fixes: 462474d760c ("target/m68k: use gdb_get_reg helpers") Fixes: a010bdbe719 ("extend GByteArray to read register helpers") Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200414163853.12164-3-philmd@redhat.com> Message-Id: <20200430190122.4592-3-alex.bennee@linaro.org>
2020-05-04target/arm: Move gen_ function typedefs to translate.hPeter Maydell
We're going to want at least some of the NeonGen* typedefs for the refactored 32-bit Neon decoder, so move them all to translate.h since it makes more sense to keep them in one group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200430181003.21682-23-peter.maydell@linaro.org
2020-05-04target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetreePeter Maydell
Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the 3-reg-same grouping to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
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