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2018-10-29target/mips: Amend MXU ASE overview noteAleksandar Markovic
Add prefix, suffix, operation descriptions, and other corrections and amendments to the comment that describes MXU ASE. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Move MXU_EN check one level higherAleksandar Markovic
Move MXU_EN check to the main MXU decoding function, to avoid code repetition. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek
Add support for emulating the S32LDD and S32LDDR MXU instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek
Adds support for emulating the Q8MUL and Q8MULSU MXU instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instruction D16MACCraig Janeczek
Add support for emulating the D16MAC MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instruction D16MULCraig Janeczek
Add support for emulating the D16MUL MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek
Add support for emulating the S8LDD MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic
Move MUL, S32M2I, S32I2M handling out of switch. These are all instructions that do not depend on MXU_EN flag of MXU_CR. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek
Add support for emulating the S32I2M and S32M2I MXU instructions. This commit also contains utility functions for reading/writing to MXU registers. This is required for overall MXU instruction support. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek
Add emulation of non-MXU MULL within MXU decoding engine. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn3'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek
Add bit encoding for MXU operand getting pattern 'optn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic
Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek
Add bit encoding for MXU accumulate add/subtract 2-bit pattern 'aptn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic
Add bit encoding for MXU accumulate add/subtract 1-bit pattern 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add MXU decoding engineAleksandar Markovic
Add MXU decoding engine: add handlers for all instruction pools, and main decode handler. The handlers, for now, for the purpose of this patch, contain only sceleton in the form of a single switch statement. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic
Provide the placeholder and add the invocation logic for MXU decoding engine. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Amend MXU instruction opcodesAleksandar Markovic
Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Define a bit for MXU in insn_flagsCraig Janeczek
Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Introduce MXU registersCraig Janeczek
Define and initialize the 16 MXU registers - 15 general computational register, and 1 control register). There is also a zero register, but it does not have any corresponding variable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-29target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder casesAleksandar Markovic
Coverity found two fallthroughs that miss break statement. Fix them. Revieved-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25target/mips: Add disassembler support for nanoMIPSAleksandar Markovic
Add disassembler support for nanoMIPS. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Matthew Fortune <matthew.fortune@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25target/mips: Implement emulation of nanoMIPS EVA instructionsDimitrije Nikolic
Implement emulation of nanoMIPS EVA instructions. They are all part of P.LS.E0 instruction pool, or one of its subpools. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25target/mips: Add nanoMIPS CRC32 instruction poolAleksandar Markovic
Add nanoMIPS CRC32 instruction pool. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-25Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' ↵Peter Maydell
into staging First RISC-V Patch Set for the 3.1 Soft Freeze This pull request contains a handful of patches that have been floating around various trees for a while but haven't made it upstream. These patches all appear quite safe. They're all somewhat independent from each other: * One refactors our IRQ management function to allow multiple interrupts to be raised an once. This patch has no functional difference. * Cleaning up the op_helper/cpu_helper split. This patch has no functional difference. * Updates to various constants to keep them in sync with the latest ISA specification and to remove some non-standard bits that snuck in. * A fix for a memory leak in the PLIC driver. * A fix to our device tree handling to avoid provinging a NULL string. I've given this my standard test: building the port, booting a Fedora root filesytem on the latest Linux tag, and then shutting down that image. Essentially I'm just following the QEMU RISC-V wiki page's instructions. Everything looks fine here. We have a lot more outstanding patches so I'll definately be submitting another PR for the soft freeze. # gpg: Signature made Wed 17 Oct 2018 21:17:52 BST # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/riscv/tags/riscv-for-master-3.1-sf0: RISC-V: Don't add NULL bootargs to device-tree RISC-V: Add missing free for plic_hart_config RISC-V: Update CSR and interrupt definitions RISC-V: Move non-ops from op_helper to cpu_helper RISC-V: Allow setting and clearing multiple irqs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging MIPS queue for October 2018 - part 2 - v2 # gpg: Signature made Wed 24 Oct 2018 14:22:54 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits) target/mips: Fix decoding of ALIGN and DALIGN instructions target/mips: Fix the title of translate.c linux-user/mips: Recognize the R5900 CPU model target/mips: Define the R5900 CPU tests/tcg/mips: Add tests for R5900 DIVU1 tests/tcg/mips: Add tests for R5900 DIV1 tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1 tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1 tests/tcg/mips: Add tests for R5900 three-operand MULTU1 tests/tcg/mips: Add tests for R5900 three-operand MULT1 tests/tcg/mips: Add tests for R5900 three-operand MULTU tests/tcg/mips: Add tests for R5900 three-operand MULT target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV target/mips: Support R5900 DIV1 and DIVU1 instructions target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions target/mips: Support R5900 three-operand MULT and MULTU instructions target/mips: Add a placeholder for R5900 MMI3 instruction subclass target/mips: Add a placeholder for R5900 MMI2 instruction subclass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24target/mips: Fix decoding of ALIGN and DALIGN instructionsAleksandar Markovic
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to allow paremeter 'bp' to occupy two and three bits, respectively. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Fix the title of translate.cAleksandar Markovic
Replace MIPS32 with MIPS, since the file covers all generations of MIPS architectures. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define the R5900 CPUFredrik Noring
The primary purpose of this change is to support programs compiled by GCC for the R5900 target and thereby run R5900 Linux distributions, for example Gentoo. GCC in version 7.3, by itself, by inspection of the GCC source code and inspection of the generated machine code, for the R5900 target, only emits two instructions that are specific to the R5900: the three- operand MULT and MULTU. GCC and libc also emit certain MIPS III instructions that are not part of the R5900 ISA. They are normally trapped and emulated by the Linux kernel, and therefore need to be treated accordingly by QEMU. A program compiled by GCC is taken to mean source code compiled by GCC under the restrictions above. One can, with the apparent limitations, with a bit of effort obtain a fully functioning operating system such as R5900 Gentoo. Strictly speaking, programs need not be compiled by GCC to make use of this change. Instructions and other facilities of the R5900 not implemented by this change are intended to signal provisional exceptions. One such example is the FPU that is not compliant with IEEE 754-1985 in system mode. It is therefore provisionally disabled. In user space the FPU is trapped and emulated by IEEE 754-1985 compliant software in the kernel, and this is handled accordingly by QEMU. Another example is the 93 multimedia instructions specific to the R5900 that generate provisional reserved instruction exception signals. One of the benefits of running a Linux distribution under QEMU is that programs can be compiled with a native compiler, where the host and target are the same, as opposed to a cross-compiler, where they are not the same. This is especially important in cases where the target hardware does not have the resources to run a native compiler. Problems with cross-compilation are often related to host and target differences in integer sizes, pointer sizes, endianness, machine code, ABI, etc. Sometimes cross-compilation is not even supported by the build script for a given package. One effective way to avoid those problems is to replace the cross-compiler with a native compiler. This change of compilation methods does not resolve the inherent problems with cross-compilation. The native compiler naturally replaces the cross-compiler, because one typically uses one or the other, and preferably the native compiler when the circumstances admit this. The native compiler is also a good test case for the R5900 QEMU user mode. Additionally, Gentoo is well- known for compiling and installing its packages from sources. This change has been tested with Gentoo compiled for R5900, including native compilation of several packages under QEMU. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user onlyFredrik Noring
The Linux kernel traps certain reserved instruction exceptions to emulate the corresponding instructions. QEMU plays the role of the kernel in user mode, so those traps are emulated by accepting the instructions. This change adds the function check_insn_opc_user_only to signal a reserved instruction exception for flagged CPUs in QEMU system mode. The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not implemented in R5900 hardware. They are trapped and emulated by the Linux kernel and, accordingly, therefore QEMU user only instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IVFredrik Noring
The R5900 is taken to be MIPS III with certain modifications. From MIPS IV it implements the instructions MOVN, MOVZ and PREF. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 DIV1 and DIVU1 instructionsFredrik Noring
Add support for DIV1 and DIVU1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructionsFredrik Noring
Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 three-operand MULT1 and MULTU1 instructionsFredrik Noring
Add support for MULT1 and MULTU1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Support R5900 three-operand MULT and MULTU instructionsFredrik Noring
The three-operand MULT and MULTU are the only R5900-specific instructions emitted by GCC 7.3. The R5900 also implements the three- operand MADD and MADDU instructions, but they are omitted in QEMU for now since they are absent in programs compiled by current GCC versions. Likewise, the R5900-specific pipeline 1 instruction variants MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are omitted here as well. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI3 instruction subclassFredrik Noring
Add a placeholder for MMI3 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI2 instruction subclassFredrik Noring
Add a placeholder for MMI2 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI1 instruction subclassFredrik Noring
Add a placeholder for MM1 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI0 instruction subclassFredrik Noring
Add a placeholder for MMI0 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 MMI instruction classFredrik Noring
Add a placeholder for MMI class. This is the main palceholder for MMI ASE. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 LQFredrik Noring
Add a placeholder for LQ instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWRFredrik Noring
Add placeholder for SQ instruction, handle RDHWR. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI3 opcode constantsFredrik Noring
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI2 opcode constantsFredrik Noring
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI1 opcode constantsFredrik Noring
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI0 opcode constantsFredrik Noring
Add definition of MI0 opcodes. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constantsFredrik Noring
Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of instructions in MMI class. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 MMI class, and LQ and SQ opcode constantsFredrik Noring
Define MMI class, LQ, and SQ R5900 opdoces. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Add R5900 Multimedia Instruction overview noteFredrik Noring
Add a comment on R5900 MMI ASE (short overview). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constantsFredrik Noring
The R5900 implements the 64-bit MIPS III instruction set except DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN, MOVZ and PREF are implemented. It has the R5900-specific three-operand instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit multimedia instructions specific to the R5900 is also implemented. The Toshiba TX System RISC TX79 Core Architecture manual: https://wiki.qemu.org/File:C790.pdf describes the C790 processor that is a follow-up to the R5900. There are a few notable differences in that the R5900 FPU - is not IEEE 754-1985 compliant, - does not implement double format, and - its machine code is nonstandard. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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