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2019-08-29target/mips: Clean up handling of CP0 register 26Aleksandar Markovic
Clean up handling of CP0 register 26. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-26-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 25Aleksandar Markovic
Clean up handling of CP0 register 25. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-25-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 24Aleksandar Markovic
Clean up handling of CP0 register 24. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-24-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 23Aleksandar Markovic
Clean up handling of CP0 register 23. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-23-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 20Aleksandar Markovic
Clean up handling of CP0 register 20. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-22-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 19Aleksandar Markovic
Clean up handling of CP0 register 19. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-21-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 18Aleksandar Markovic
Clean up handling of CP0 register 18. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 17Aleksandar Markovic
Clean up handling of CP0 register 17. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-19-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 16Aleksandar Markovic
Clean up handling of CP0 register 16. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-18-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 15Aleksandar Markovic
Clean up handling of CP0 register 15. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-17-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 14Aleksandar Markovic
Clean up handling of CP0 register 14. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-16-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 13Aleksandar Markovic
Clean up handling of CP0 register 13. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-15-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 12Aleksandar Markovic
Clean up handling of CP0 register 12. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-14-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 11Aleksandar Markovic
Clean up handling of CP0 register 11. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-13-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 10Aleksandar Markovic
Clean up handling of CP0 register 10. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-12-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 9Aleksandar Markovic
Clean up handling of CP0 register 9. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 8Aleksandar Markovic
Clean up handling of CP0 register 8. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 7Aleksandar Markovic
Clean up handling of CP0 register 7. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 6Aleksandar Markovic
Clean up handling of CP0 register 6. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 5Aleksandar Markovic
Clean up handling of CP0 register 5. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 4Aleksandar Markovic
Clean up handling of CP0 register 4. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 3Aleksandar Markovic
Clean up handling of CP0 register 3. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 2Aleksandar Markovic
Clean up handling of CP0 register 2. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 1Aleksandar Markovic
Clean up handling of CP0 register 1. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29target/mips: Clean up handling of CP0 register 0Aleksandar Markovic
Clean up handling of CP0 register 0. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-29powerpc/spapr: Add host threads parameter to ibm,get_system_parameterSuraj Jitindar Singh
The ibm,get_system_parameter rtas call is used by the guest to retrieve data relating to certain parameters of the system. The SPLPAR characteristics option (token 20) is used to determine characteristics of the environment in which the lpar will run. It may be useful for a guest to know the number of physical host threads present on the underlying system where it is being run. Add the characteristic "HostThrs" to the SPLPAR Characteristics ibm,get_system_parameter rtas call to expose this information to a guest. Add a n_host_threads property to the processor class which is then used to retrieve this information and define it for POWER8 and POWER9. Other processors will default to 0 and the charateristic won't be added. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190827045751.22123-1-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29target/ppc: Refactor emulation of vmrgew and vmrgow instructionsStefan Brankovic
Since I found this two instructions implemented with tcg, I refactored them so they are consistent with other similar implementations that I introduced in this patch. Also, a new dual macro GEN_VXFORM_TRANS_DUAL is added. This macro is used if one instruction is realized with direct translation, and second one with a helper. Signed-off-by: Stefan Brankovic <stefan.brankovic@rt-rk.com> Message-Id: <1566898663-25858-4-git-send-email-stefan.brankovic@rt-rk.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29target/ppc: Fix do_float_check_status vs inexactRichard Henderson
The underflow and inexact exceptions are not mutually exclusive. Check for both of them. Tidy the reset of FPSCR[FI]. Fixes: https://bugs.launchpad.net/bugs/1841442 Reported-by: Paul Clarke <pc@us.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Paul Clarke <pc@us.ibm.com> Message-Id: <20190826165434.18403-2-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29target/ppc: Set float_tininess_before_rounding at cpu resetRichard Henderson
As defined in Power 3.0 section 4.4.4 "Underflow Exception", a tiny result is detected before rounding. Fixes: https://bugs.launchpad.net/qemu/+bug/1841491 Reported-by: Paul Clarke <pc@us.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190827020013.27154-1-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29ppc: Fix xscvdpspn for SNANPaul A. Clarke
The xscvdpspn instruction implements a non-arithmetic conversion. In particular, NaNs are not silenced and rounding is not performed. Rewrite to match the pseudocode for ConvertDPtoSP_NS() in the Power 3.0B manual. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Message-Id: <1566321964-1447-1-git-send-email-pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Replaced description with clearer version from rth] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29ppc: Fix xsmaddmdp and friendsPaul A. Clarke
A class of instructions of the form: op Target,A,B which operate like: Target = Target * A + B have a bit set which distinguishes them from instructions that operate as: Target = Target * B + A This bit is not being checked properly (using PPC_BIT macro), so all instructions in this class are operating incorrectly as the second form above. The bit was being checked as if it were part of a 64-bit instruction opcode, rather than a proper 32-bit opcode. Fix by using the macro (PPC_BIT32) which treats the opcode as a 32-bit quantity. Fixes: c9f4e4d8b632 ("target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro") Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Message-Id: <1566401321-22419-1-git-send-email-pc@us.ibm.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-25target/alpha: fix tlb_fill trap_arg2 value for instruction fetchAurelien Jarno
Commit e41c94529740cc26 ("target/alpha: Convert to CPUClass::tlb_fill") slightly changed the way the trap_arg2 value is computed in case of TLB fill. The type of the variable used in the ternary operator has been changed from an int to an enum. This causes the -1 value to not be sign-extended to 64-bit in case of an instruction fetch. The trap_arg2 ends up with 0xffffffff instead of 0xffffffffffffffff. Fix that by changing the -1 into -1LL. This fixes the execution of user space processes in qemu-system-alpha. Fixes: e41c94529740cc26 Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [rth: Test MMU_DATA_LOAD and MMU_DATA_STORE instead of implying them.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-08-23Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into stagingPeter Maydell
s390x updates: - fix a bug in tcg vector handling - improved skey handling # gpg: Signature made Thu 22 Aug 2019 14:43:30 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190822: s390x/mmu: Factor out storage key handling s390x/mmu: Better storage key reference and change bit handling s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE s390x/tcg: Rework MMU selection for instruction fetches s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() s390x/mmu: Trace the right value if setting/getting the storage key fails s390x/tcg: Fix VERIM with 32/64 bit elements Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-08-22Merge remote-tracking branch ↵Peter Maydell
'remotes/bkoppelmann2/tags/pull-tricore-20190822-1' into staging Converted target/tricore to translate_loop # gpg: Signature made Thu 22 Aug 2019 11:17:37 BST # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full] # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann2/tags/pull-tricore-20190822-1: target/tricore: Fix tricore_tr_translate_insn target/tricore: Implement a qemu excptions helper target/tricore: Use translate_loop target-tricore: Make env a member of DisasContext target/tricore: Use DisasContextBase API Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-08-22s390x/mmu: Factor out storage key handlingDavid Hildenbrand
Factor it out, add a comment how it all works, and also use it in the REAL MMU. Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190816084708.602-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22s390x/mmu: Better storage key reference and change bit handlingDavid Hildenbrand
Any access sets the reference bit. In case we have a read-fault, we should not allow writes to the TLB entry if the change bit was not already set. This is a preparation for proper storage-key reference/change bit handling in TCG and a fix for KVM whereby read accesses would set the change bit (old KVM versions without the ioctl to carry out the translation). Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190816084708.602-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBEDavid Hildenbrand
Whenever we modify a storage key, we should flush the TLBs of all CPUs, so the MMU fault handling code can properly consider the changed storage key (to e.g., properly set the reference and change bit on the next accesses). These functions are barely used in modern Linux guests, so the performance implications are neglectable for now. This is a preparation for better reference and change bit handling for TCG, which will require more MMU changes. Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190816084708.602-5-david@redhat.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22s390x/tcg: Rework MMU selection for instruction fetchesDavid Hildenbrand
Instructions are always fetched from primary address space, except when in home address mode. Perform the selection directly in cpu_mmu_index(). get_mem_index() is only used to perform data access, instructions are fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true). We don't care about restricting the access permissions of the TLB entries anymore, as we no longer enter PRIMARY entries into the SECONDARY MMU. Cleanup related code a bit. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20190816084708.602-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug()David Hildenbrand
Let's select the ASC before calling the function. This is a prepararion to remove the ASC magic depending on the access mode from mmu_translate. There is currently no way to distinguish if we have code or data access. For now, we were using code access, because especially when debugging with the gdbstub, we want to read and disassemble what we single-step. Note: KVM guest can now no longer be crashed using qmp/hmp/gdbstub if they happen to be in AR mode. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190816084708.602-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22s390x/mmu: Trace the right value if setting/getting the storage key failsDavid Hildenbrand
We want to trace the actual return value, not "0". Fixes: 0f5f669147b5 ("s390x: Enable new s390-storage-keys device") Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190816084708.602-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22s390x/tcg: Fix VERIM with 32/64 bit elementsDavid Hildenbrand
Wrong order of operands. The constant always comes last. Makes QEMU crash reliably on specific git fetch invocations. Reported-by: Stefano Brivio <sbrivio@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190814151242.27199-1-david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Fixes: 5c4b0ab460ef ("s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK") Cc: qemu-stable@nongnu.org Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-08-22target/tricore: Fix tricore_tr_translate_insnBastian Koppelmann
we now fetch 2 bytes first, check whether we have a 32 bit insn, and only then fetch another 2 bytes. We also make sure that a 16 bit insn that still fits into the current page does not end up in the next page. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-08-22target/tricore: Implement a qemu excptions helperBastian Koppelmann
this helper is only used to raise qemu specific exceptions. We use this helper to raise it on breakpoints. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-08-22target/tricore: Use translate_loopBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-08-22target-tricore: Make env a member of DisasContextBastian Koppelmann
otherwise we have to pass env down through all functions which blocks the usage of translator_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-08-22target/tricore: Use DisasContextBase APIBastian Koppelmann
this gets rid of the copied fields of TriCore's DisasContext and now uses the shared DisasContextBase, which is necessary for the conversion to translate_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-08-22Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' ↵Peter Maydell
into staging Monitor patches for 2019-08-21 # gpg: Signature made Wed 21 Aug 2019 16:35:07 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-monitor-2019-08-21: monitor/qmp: Update comment for commit 4eaca8de268 qdev: Collect HMP handlers command handlers in qdev-monitor.c qapi: Move query-target from misc.json to machine.json hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-08-21Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-pull-request' into staging Various trivial fixes # gpg: Signature made Wed 21 Aug 2019 12:19:11 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: hw/display: Compile various display devices as common object hw/display/sm501: Remove unused include spapr_events: Rewrite a fall through comment vl: Rewrite a fall through comment target/ppc: Rewrite a fall through comment hw/ipmi: Rewrite a fall through comment hw/dma/omap_dma: Move switch 'fall through' comment to correct place json: Move switch 'fall through' comment to correct place hw/net/e1000: Fix erroneous comment .gitignore: ignore some vhost-user* related files configure: fix sdl detection using sdl2-config configure: remove obsoleted $sparc_cpu variable misc: fix naming scheme of compatiblity arrays test: Use g_strndup instead of plain strndup Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-08-21Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20190821' ↵Peter Maydell
into staging ppc patch queue for 2019-08-21 First ppc and spapr pull request for qemu-4.2. Includes: * Some TCG emulation fixes and performance improvements * Support for the mffsl instruction in TCG * Added missing DPDES SPR * Some enhancements to the emulation of the XIVE interrupt controller * Cleanups to spapr MSI management * Some new suspend/resume infrastructure and a draft suspend implementation for spapr * New spapr hypercall for TPM communication (will be needed for secure guests under an Ultravisor) * Fix several memory leaks And a few other assorted fixes. # gpg: Signature made Wed 21 Aug 2019 08:24:44 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.2-20190821: (42 commits) ppc: Fix emulated single to double denormalized conversions ppc: Fix emulated INFINITY and NAN conversions ppc: conform to processor User's Manual for xscvdpspn ppc: Add support for 'mffsl' instruction target/ppc: Add Directed Privileged Door-bell Exception State (DPDES) SPR spapr/xive: Mask the EAS when allocating an IRQ spapr: Implement better workaround in spapr-vty device spapr/irq: Drop spapr_irq_msi_reset() spapr/pci: Free MSIs during reset spapr/pci: Consolidate de-allocation of MSIs ppc: remove idle_timer logic spapr: Implement ibm,suspend-me i386: use machine class ->wakeup method machine: Add wakeup method to MachineClass ppc/xive: Improve 'info pic' support ppc/xive: Provide silent escalation support ppc/xive: Provide unconditional escalation support ppc/xive: Provide escalation support ppc/xive: Provide backlog support ppc/xive: Implement TM_PULL_OS_CTX special command ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster
Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190709152053.16670-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Rebased onto merge commit 95a9457fd44; missed instances of qom/cpu.h in comments replaced]
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