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2017-06-06Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86 and machine queue, 2017-06-05 # gpg: Signature made Mon 05 Jun 2017 19:58:01 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: scripts: Test script to look for -device crashes qemu.py: Add QEMUMachine.exitcode() method qemu.py: Don't set _popen=None on error/shutdown spapr: cleanup spapr_fixup_cpu_numa_dt() usage numa: move numa_node from CPUState into target specific classes numa: make hmp 'info numa' fetch numa nodes from qmp_query_cpus() result numa: make sure that all cpus have has_node_id set if numa is enabled numa: move default mapping init to machine numa: consolidate cpu_preplug fixups/checks for pc/arm/spapr pc: Use "min-[x]level" on compat_props Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-05numa: move numa_node from CPUState into target specific classesIgor Mammedov
Move vcpu's associated numa_node field out of generic CPUState into inherited classes that actually care about cpu<->numa mapping, i.e: ARMCPU, PowerPCCPU, X86CPU. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1496161442-96665-6-git-send-email-imammedo@redhat.com> [ehabkost: s/CPU is belonging to/CPU belongs to/ on comments] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-06-05target/alpha: Use goto_tb for fallthru between TBsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/alpha: Implement WTINT inlineRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/mips: optimize indirect branchesAurelien Jarno
Cc: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170430145254.25616-4-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/mips: optimize cross-page direct jumps in softmmuAurelien Jarno
Cc: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170430145254.25616-3-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/aarch64: optimize indirect branchesEmilio G. Cota
Measurements: [Baseline performance is that before applying this and the previous commit] - NBench, aarch64-softmmu. Host: Intel i7-4790K @ 4.00GHz 1.7x +-+--------------------------------------------------------------------------------------------------------------+-+ | | | cross | 1.6x +cross+jr.................................................####...................................................+-+ | #++# | | # # | 1.5x +-+...................................................*****..#...................................................+-+ | *+++* # | | * * # | 1.4x +-+...................................................*...*..#...................................................+-+ | * * # | | ##### * * # | 1.3x +-+................................****+++#...........*...*..#...................................................+-+ | *++* # * * # | | * * # * * # | 1.2x +-+................................*..*...#...........*...*..#...................................................+-+ | * * # * * # | | #### * * # * * # | 1.1x +-+.......................+++#..#..*..*...#...........*...*..#...................................................+-+ | **** # * * # * * # ****#### | | * * # * * # * * # ****### +++#### ****### * * # | 1x +-++-++++++-++++****###++-*++*++#++*++*+-+#++****+++++*+++*++#++*++*-+#++*****++#++****###-++*++*-+#++*+-*+++#+-++-+ | *****### * * # * * # * * # *++*### * * # * * # * * # * *++# * * # * * # | | * *++# * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # | 0.9x +-+---*****###--****###---****###--****####--****###--*****###--****###--*****###--****###---****###--****####---+-+ ASSIGNMENT BITFIELD FOURFP EMULATION HUFFMAN LU DECOMPOSITIONNEURAL NUMERIC SORSTRING SORT hmean png: http://imgur.com/qO9ubtk NB. cross here represents the previous commit. - SPECint06 (test set), aarch64-linux-user. Host: Intel i7-4790K @ 4.00GHz 1.5x +-+--------------------------------------------------------------------------------------------------------------+-+ | ***** | | *+++* jr | | * * | 1.4x +-+.....................................................................*...*.....................+++............+-+ | * * | | | ***** * * | | | * * * * ***** | 1.3x +-+....................................*...*............................*...*....................*.|.*...........+-+ | +++ * * * * * | * | | ***** * * * * *+++* | | * * * * * * * * | 1.2x +-+....................*...*...........*...*............................*...*...........*****....*...*...........+-+ | ***** * * * * * * * * * * +++ | | * * * * * * * * * * * * ***** | | * * * * ***** * * * * * * * * * * | 1.1x +-+...*...*............*...*...*...*...*...*............................*...*....+++....*...*....*...*...*...*...+-+ | * * * * * * * * * * ***** * * * * * * | | * * * * * * * * ***** * * * * * * * * * * | | * * ***** * * * * * * * * ****** * * * * * * * * * * | 1x +-++-+*+++*-++*+++*++++*+-+*+++*-++*+++*-++*+++*+++*++-*++++*-++*****+++*++-*+++*++-*+++*+-+*++++*+++*++-*+++*+-++-+ | * * * * * * * * * * * * * * *+++* * * * * * * * * * * | | * * * * * * * * * * * * * * * * * * * * * * * * * * | | * * * * * * * * * * * * * * * * * * * * * * * * * * | 0.9x +-+---*****---*****----*****---*****---*****---*****---******---*****---*****---*****---*****----*****---*****---+-+ astar bzip2 gcc gobmk h264ref hmmlibquantum mcf omnetpperlbench sjengxalancbmk hmean png: http://imgur.com/3Dp4vvq - SPECint06 (train set), aarch64-linux-user. Host: Intel i7-4790K @ 4.00GHz 1.7x +-+--------------------------------------------------------------------------------------------------------------+-+ | | | jr | 1.6x +-+...............................................................................................+++............+-+ | ***** | | *+++* | | * * | 1.5x +-+..............................................................................................*...*...........+-+ | +++ * * | | ***** * * | 1.4x +-+.....................................................................*+++*....................*...*...........+-+ | * * * * | | ***** * * * * | | * * * * ***** * * | 1.3x +-+....................................*...*............................*...*...*...*............*...*...........+-+ | +++ * * * * * * * * | | ***** * * * * * * ***** * * | 1.2x +-+....................*...*...........*...*............................*...*...*...*...*+++*....*...*...*****...+-+ | * * * * * * * * * * * * *+++* | | ***** * * ***** * * * * * * * * * * * * | | * * * * *+++* * * * * * * * * * * * * | 1.1x +-+...*...*............*...*...*...*...*...*............................*...*...*...*...*...*....*...*...*...*...+-+ | * * ***** * * * * * * ***** * * * * * * * * * * | | * * * * * * * * * * +++ ****** *+++* * * * * * * * * * * | 1x +-+---*****---*****----*****---*****---*****---*****---******---*****---*****---*****---*****----*****---*****---+-+ astar bzip2 gcc gobmk h264ref hmmlibquantum mcf omnetpperlbench sjengxalancbmk hmean png: http://imgur.com/vRrdc9j Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/aarch64: optimize cross-page direct jumps in softmmuEmilio G. Cota
Perf numbers in next commit's log. Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/hppa: Use tcg_gen_lookup_and_goto_ptrRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/s390: Use tcg_gen_lookup_and_goto_ptrRichard Henderson
Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/i386: optimize indirect branchesEmilio G. Cota
Speed up indirect branches by jumping to the target if it is valid. Softmmu measurements (see later commit for user-mode numbers): Note: baseline (i.e. speedup == 1x) is QEMU v2.9.0. - SPECint06 (test set), x86_64-softmmu (Ubuntu 16.04 guest). Host: Intel i7-4790K @ 4.00GHz 2.4x +-+--------------------------------------------------------------------------------------------------------------+-+ | | | cross | 2.2x +cross+jr..........................................................................+++...........................+-+ | | | | +++ | | 2x +-+..............................................................................|..|............................+-+ | | | | | | | | 1.8x +-+..............................................................................|####...........................+-+ | |# |# | | **** |# | 1.6x +-+............................................................................*.|*.|#...........................+-+ | * |* |# | | * |* |# | 1.4x +-+.......................................................................+++..*.|*.|#...........................+-+ | ++++++ #### * |*++# +++ | | +++ | | #++# *++* # +++ | | 1.2x +-+......................###.....####....+++............|..|...........****..#.*..*..#....####...|.###.....####..+-+ | +++ **** # **** # #### ***### *++* # * * # #++# ****|# +++#++# | | ****### +++ *++* # *++* # ++# # #### *|* |# +++ * * # * * # *** # *| *|# **** # | 1x +-++-*++*++#++***###++*++*+#++*+-*++#+****++#++***++#+-*+*++#-+****##++*++*-+#+*++*-+#++*+*++#++*-+*+#++*++*++#-++-+ | * * # * * # * * # * * # * * # * * # *|* |# *++* # * * # * * # * * # * * # * * # | | * * # * * # * * # * * # * * # * * # *+*++# * * # * * # * * # * * # * * # * * # | 0.8x +-+--****###--***###--****##--****###-****###--***###--***###--****##--****###-****###--***###--****##--****###--+-+ astar bzip2 gcc gobmk h264ref hmmlibquantum mcf omnetpperlbench sjengxalancbmk hmean png: http://imgur.com/DU36YFU NB. 'cross' represents the previous commit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-11-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/i386: optimize cross-page direct jumps in softmmuEmilio G. Cota
Instead of unconditionally exiting to the exec loop, use the gen_jr helper to jump to the target if it is valid. Perf impact: see next commit's log. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-10-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/i386: introduce gen_jr helper to generate lookup_and_goto_ptrEmilio G. Cota
This helper will be used by subsequent changes. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-9-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/arm: optimize indirect branchesEmilio G. Cota
Speed up indirect branches by jumping to the target if it is valid. Softmmu measurements (see later commit for user-mode results): Note: baseline (i.e. speedup == 1x) is QEMU v2.9.0. - Impact on Boot time | setup | ARM debian jessie boot+shutdown time | stddev | |--------+--------------------------------------+--------| | v2.9.0 | 8.84 | 0.07 | | +cross | 8.85 | 0.03 | | +jr | 8.83 | 0.06 | - NBench, arm-softmmu (debian jessie guest). Host: Intel i7-4790K @ 4.00GHz 1.3x +-+-------------------------------------------------------------------------------------------------------------+-+ | | | cross #### | 1.25x +cross+jr..........................................................#++#.........................................+-+ | #### # # | | +++# # # # | | +++ **** # # # | 1.2x +-+...................................####............*..*..#......#..#.........................................+-+ | **** # * * # # # #### | | * * # * * # # # # # | 1.15x +-+................................*..*..#............*..*..#......#..#.....#..#................................+-+ | * * # * * # # # # # | | * * # #### * * # # # # # | | * * # # # * * # # # # # #### | 1.1x +-+................................*..*..#......#..#..*..*..#......#..#.....#..#.........................#..#...+-+ | * * # # # * * # # # # # # # | | * * # # # * * # # # # # # # | 1.05x +-+..........................####..*..*..#......#..#..*..*..#......#..#.....#..#......+++............*****..#...+-+ | ***** # * * # # # * * # ***** # # # +++ | ****### * * # | | *+++* # * * # # # * * # *+++* # **** # *****### * * # * * # | | *****### +++#### * * # * * # ***** # * * # * * # * * # * | *++# * * # * * # | 1x +-++-+*+++*-+#++****++#++*+-+*++#+-*++*++#-+*+++*-+#++*++*++#++*+-+*++#+-*++*++#-+*+++*-+#++*++*++#++*+-+*++#+-++-+ | * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # | | * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # | 0.95x +-+---*****###--****###--*****###--****###--*****###--****###--*****###--****###--*****###--****###--*****###---+-+ ASSIGNMENT BITFIELD FOURFP EMULATION HUFFMAN LU DECOMPOSITIONEURAL NNUMERIC SOSTRING SORT hmean png: http://imgur.com/eOLmZNR NB. 'cross' represents the previous commit. Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-8-git-send-email-cota@braap.org> [rth: Replace gen_jr global variable with DISAS_EXIT state.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/arm: optimize cross-page direct jumps in softmmuEmilio G. Cota
Instead of unconditionally exiting to the exec loop, use the lookup_and_goto_ptr helper to jump to the target if it is valid. Perf impact: see next commit's log. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-7-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/nios2: Fix 64-bit ilp32 compilationRichard Henderson
Avoid a "cast from pointer to integer of different size" warning by using the proper host type. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-04target/arm: add data cache invalidation cp15 instruction to cortex-r5Luc MICHEL
The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the data cache on the cortex-r5. Implementing it as a NOP. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-06-02Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170601' ↵Peter Maydell
into staging migration/next for 20170601 # gpg: Signature made Thu 01 Jun 2017 17:51:04 BST # gpg: using RSA key 0xF487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" # gpg: aka "Juan Quintela <quintela@trasno.org>" # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/juanquintela/tags/migration/20170601: migration: Move include/migration/block.h into migration/ migration: Export ram.c functions in its own file migration: Create include for migration snapshots migration: Export rdma.c functions in its own file migration: Export tls.c functions in its own file migration: Export socket.c functions in its own file migration: Export fd.c functions in its own file migration: Export exec.c functions in its own file migration: Split qemu-file.h migration: Remove unneeded includes of migration/vmstate.h migration: shut src return path unconditionally migration: fix leak of src file on dst migration: Remove section_id parameter from vmstate_load migration: loadvm handlers are not used migration: Use savevm_handlers instead of loadvm copy Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02arm: Implement HFNMIENA support for M profile MPUPeter Maydell
Implement HFNMIENA support for the M profile MPU. This bit controls whether the MPU is treated as enabled when executing at execution priorities of less than zero (in NMI, HardFault or with the FAULTMASK bit set). Doing this requires us to use a different MMU index for "running at execution priority < 0", because we will have different access permissions for that case versus the normal case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-14-git-send-email-peter.maydell@linaro.org
2017-06-02arm: add MPU support to M profile CPUsMichael Davidsaver
The M series MPU is almost the same as the already implemented R profile MPU (v7 PMSA). So all we need to implement here is the MPU register interface in the system register space. This implementation has the same restriction as the R profile MPU that it doesn't permit regions to be sized down smaller than 1K. We also do not yet implement support for MPU_CTRL.HFNMIENA; this bit should if zero disable use of the MPU when running HardFault, NMI or with FAULTMASK set to 1 (ie at an execution priority of less than zero) -- if the MPU is enabled we don't treat these cases any differently. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1493122030-32191-13-git-send-email-peter.maydell@linaro.org [PMM: Keep all the bits in mpu_ctrl field, rather than using SCTLR bits for them; drop broken HFNMIENA support; various cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02armv7m: Classify faults as MemManage or BusFaultMichael Davidsaver
General logic is that operations stopped by the MPU are MemManage, and those which go through the MPU and are caught by the unassigned handle are BusFault. Distinguish these by looking at the exception.fsr values, and set the CFSR bits and (if appropriate) fill in the BFAR or MMFAR with the exception address. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1493122030-32191-12-git-send-email-peter.maydell@linaro.org [PMM: i-side faults do not set BFAR/MMFAR, only d-side; added some CPU_LOG_INT logging] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02arm: All M profile cores are PMSAPeter Maydell
All M profile CPUs are PMSA, so set the feature bit. (We haven't actually implemented the M profile MPU register interface yet, but setting this feature bit gives us closer to correct behaviour for the MPU-disabled case.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-11-git-send-email-peter.maydell@linaro.org
2017-06-02armv7m: Implement M profile default memory mapMichael Davidsaver
Add support for the M profile default memory map which is used if the MPU is not present or disabled. The main differences in behaviour from implementing this correctly are that we set the PAGE_EXEC attribute on the right regions of memory, such that device regions are not executable. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1493122030-32191-10-git-send-email-peter.maydell@linaro.org [PMM: rephrased comment and commit message; don't mark the flash memory region as not-writable; list all the cases in the default map explicitly rather than using a 'default' case for the non-executable regions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02armv7m: Improve "-d mmu" tracing for PMSAv7 MPUMichael Davidsaver
Improve the "-d mmu" tracing for the PMSAv7 MPU translation process as an aid in debugging guest MPU configurations: * fix a missing newline for a guest-error log * report the region number with guest-error or unimp logs of bad region register values * add a log message for the overall result of the lookup * print "0x" prefix for hex values Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-9-git-send-email-peter.maydell@linaro.org [PMM: a little tidyup, report region number in all messages rather than just one] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02arm: Remove unnecessary check on cpu->pmsav7_dregionPeter Maydell
Now that we enforce both: * pmsav7_dregion == 0 implies has_mpu == false * PMSA with has_mpu == false means SCTLR.M cannot be set we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(), because we can only reach this code path if the MPU is enabled (and so region_translation_disabled() returned false). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-8-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Don't let no-MPU PMSA cores write to SCTLR.MPeter Maydell
If the CPU is a PMSA config with no MPU implemented, then the SCTLR.M bit should be RAZ/WI, so that the guest can never turn on the non-existent MPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Don't clear ARM_FEATURE_PMSA for no-mpu configsPeter Maydell
Fix the handling of QOM properties for PMSA CPUs with no MPU: Allow no-MPU to be specified by either: * has-mpu = false * pmsav7_dregion = 0 and make setting one imply the other. Don't clear the PMSA feature bit in this situation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-6-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Clean up handling of no-MPU PMSA CPUsPeter Maydell
ARM CPUs come in two flavours: * proper MMU ("VMSA") * only an MPU ("PMSA") For PMSA, the MPU may be implemented, or not (in which case there is default "always acts the same" behaviour, but it isn't guest programmable). QEMU is a bit confused about how we indicate this: we have an ARM_FEATURE_MPU, but it's not clear whether this indicates "PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we use it for one purpose and sometimes the other. Currently trying to implement a PMSA-without-MPU core won't work correctly because we turn off the ARM_FEATURE_MPU bit and then a lot of things which should still exist get turned off too. As the first step in cleaning this up, rename the feature bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with or without MPU). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-5-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Use different ARMMMUIdx values for M profilePeter Maydell
Make M profile use completely separate ARMMMUIdx values from those that A profile CPUs use. This is a prelude to adding support for the MPU and for v8M, which together will require 6 MMU indexes which don't map cleanly onto the A profile uses: non secure User non secure Privileged non secure Privileged, execution priority < 0 secure User secure Privileged secure Privileged, execution priority < 0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-4-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Add support for M profile CPUs having different MMU index semanticsPeter Maydell
The M profile CPU's MPU has an awkward corner case which we would like to implement with a different MMU index. We can avoid having to bump the number of MMU modes ARM uses, because some of our existing MMU indexes are only used by non-M-profile CPUs, so we can borrow one. To avoid that getting too confusing, clean up the code to try to keep the two meanings of the index separate. Instead of ARMMMUIdx enum values being identical to core QEMU MMU index values, they are now the core index values with some high bits set. Any particular CPU always uses the same high bits (so eventually A profile cores and M profile cores will use different bits). New functions arm_to_core_mmu_idx() and core_to_arm_mmu_idx() convert between the two. In general core index values are stored in 'int' types, and ARM values are stored in ARMMMUIdx types. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-3-git-send-email-peter.maydell@linaro.org
2017-06-02arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()Peter Maydell
When identifying the DFSR format for an alignment fault, use the mmu index that we are passed, rather than calling cpu_mmu_index() to get the mmu index for the current CPU state. This doesn't actually make any difference since the only cases where the current MMU index differs from the index used for the load are the "unprivileged load/store" instructions, and in that case the mmu index may differ but the translation regime is the same (apart from the "use from Hyp mode" case which is UNPREDICTABLE). However it's the more logical thing to do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-2-git-send-email-peter.maydell@linaro.org
2017-06-02target/arm: clear PMUVER field of AA64DFR0 when vPMU=offWei Huang
The PMUv3 driver of linux kernel (in arch/arm64/kernel/perf_event.c) relies on the PMUVER field of id_aa64dfr0_el1 to decide if PMU support is present or not. This patch clears the PMUVER field under TCG mode when vPMU=off. Without it, PMUv3 will init insider guest VMs even with vPMU=off. This patch also removes a redundant line inside the if-statement. Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1495123889-32301-1-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-01migration: Remove unneeded includes of migration/vmstate.hJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-05-30target/sh4: fix RTE instruction delay slotAurelien Jarno
The ReTurn from Exception (RTE) instruction loads the system register (SR) with the saved system register (SSR). It has a delay slot, and behaves specially according to the SH4 manual: The SR value accessed by the instruction in the RTE delay slot is the value restored from SSR by the RTE instruction. The SR and MD values defined prior to RTE execution are used to fetch the instruction in the RTE delay slot. The instruction in the delay slot being often a NOP, it doesn't cause any issue most of the time except in some rare cases where the NOP is being splitted in a different TB (for example when the TCG op buffer is full). In that case the NOP is fetched with the user permissions and causes an instruction TLB protection violation exception. This patches fixes that by introducing a new delay slot flag for the RTE instruction. Given it's a privileged instruction, the RTE delay slot instruction is always fetched in privileged mode. It is therefore enough to to check for this flag in cpu_mmu_index. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-05-30target/sh4: ignore interrupts in a delay slotAurelien Jarno
Delay slots are indivisible, therefore avoid scheduling an interrupt in the delay slot. However exceptions are possible. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-05-30target/sh4: introduce DELAY_SLOT_MASKAurelien Jarno
This will make easier the introduction of a new flag in the next patches. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-05-30target/sh4: fix reset when using a kernel and an initrdAurelien Jarno
When a masked exception happens, the SH4 CPU generates a non-masked reset exception, which then jumps to the reset vector at address 0xA0000000. While this is emulated correctly in QEMU, this does not work when using a kernel and initrd as this address then contain an illegal instruction (and there is no guarantee the kernel and initrd haven't been overwritten). Therefore call qemu_system_reset_request to reload the kernel and initrd and load the program counter to the kernel entry point. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-05-30target/sh4: log unauthorized accesses using qemu_log_maskAurelien Jarno
qemu_log_mask() is preferred over fprintf() for logging errors. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-05-30Merge remote-tracking branch 'dgibson/tags/ppc-for-2.10-20170525' into stagingStefan Hajnoczi
ppc patch queue 2017-05-25 Assorted accumulated patches. These are nearly all bugfixes at one level or another - some for longstanding problems, others for some regressions caused by more recent cleanups. This includes preliminary patches towards fixing migration for Radix Page Table guests under POWER9 and also fixing some migration regressions due to the re-organization of the interrupt controller code. Not all the pieces are there yet, so those still won't quite work, but the preliminary changes make sense on their own. # gpg: Signature made Thu 25 May 2017 04:50:00 AM BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * dgibson/tags/ppc-for-2.10-20170525: xics: add unrealize handler hw/ppc/spapr.c: recover pending LMB unplug info in spapr_lmb_release hw/ppc: migrating the DRC state of hotplugged devices hw/ppc: removing drc->detach_cb and drc->detach_cb_opaque hw/ppc/spapr.c: adding pending_dimm_unplugs to sPAPRMachineState spapr: add pre_plug function for memory pseries: Restore support for total vcpus not a multiple of threads-per-core for old machine types pseries: Split CAS PVR negotiation out into a separate function spapr: fix error reporting in xics_system_init() spapr_cpu_core: drop reference on ICP object during CPU realization hw/ppc/spapr_events.c: removing 'exception' from sPAPREventLogEntry spapr: ensure core_slot isn't NULL in spapr_core_unplug() xics_kvm: cache already enabled vCPU ids spapr: Consolidate HPT freeing code into a routine spapr-cpu-core: release ICP object when realization fails spapr: sanitize error handling in spapr_ics_create() ppc/xics: simplify prototype of xics_spapr_init() target/ppc: reset reservation in do_rfi() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-05-30Merge remote-tracking branch 'armbru/tags/pull-qapi-2017-05-23' into stagingStefan Hajnoczi
QAPI patches for 2017-05-23 # gpg: Signature made Tue 23 May 2017 12:33:32 PM BST # gpg: using RSA key 0x3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * armbru/tags/pull-qapi-2017-05-23: qapi-schema: Remove obsolete note from ObjectTypeInfo block: Use QDict helpers for --force-share shutdown: Expose bool cause in SHUTDOWN and RESET events shutdown: Add source information to SHUTDOWN and RESET shutdown: Preserve shutdown cause through replay shutdown: Prepare for use of an enum in reset/shutdown_request shutdown: Simplify shutdown_signal sockets: Plug memory leak in socket_address_flatten() scripts/qmp/qom-set: fix the value argument passed to srv.command() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-05-24target/ppc: reset reservation in do_rfi()Nikunj A Dadhania
For transitioning back to userspace after the interrupt. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-05-23shutdown: Add source information to SHUTDOWN and RESETEric Blake
Time to wire up all the call sites that request a shutdown or reset to use the enum added in the previous patch. It would have been less churn to keep the common case with no arguments as meaning guest-triggered, and only modified the host-triggered code paths, via a wrapper function, but then we'd still have to audit that I didn't miss any host-triggered spots; changing the signature forces us to double-check that I correctly categorized all callers. Since command line options can change whether a guest reset request causes an actual reset vs. a shutdown, it's easy to also add the information to reset requests. Signed-off-by: Eric Blake <eblake@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> [ppc parts] Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> [SPARC part] Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x parts] Message-Id: <20170515214114.15442-5-eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2017-05-19s390/kvm: do not reset riccb on initial cpu resetChristian Borntraeger
The riccb is kept unchanged during initial cpu reset. Move the data structure to the other registers that are unchanged. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-05-19s390x/css: ccw translation infrastructureXiao Feng Ren
Implement a basic infrastructure of handling channel I/O instruction interception for passed through subchannels: 1. Branch the code path of instruction interception handling by SubChannel type. 2. For a passed-through subchannel, issue the ORB to kernel to do ccw translation and perform an I/O operation. 3. Assign different condition code based on the I/O result, or trigger a program check. Signed-off-by: Xiao Feng Ren <renxiaof@linux.vnet.ibm.com> Signed-off-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Message-Id: <20170517004813.58227-12-bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-05-19s390x/css: add s390-squash-mcss machine optionXiao Feng Ren
We want to support real (i.e. not virtual) channel devices even for guests that do not support MCSS-E (where guests may see devices from any channel subsystem image at once). As all virtio-ccw devices are in css 0xfe (and show up in the default css 0 for guests not activating MCSS-E), we need an option to squash both the virtio subchannels and e.g. passed-through subchannels from their real css (0-3, or 0 for hosts not activating MCSS-E) into the default css. This will be exploited in a later patch. Signed-off-by: Xiao Feng Ren <renxiaof@linux.vnet.ibm.com> Signed-off-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Message-Id: <20170517004813.58227-4-bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-05-18Merge remote-tracking branch 'quintela/tags/migration/20170517' into stagingStefan Hajnoczi
migration/next for 20170517 # gpg: Signature made Wed 17 May 2017 11:46:36 AM BST # gpg: using RSA key 0xF487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" # gpg: aka "Juan Quintela <quintela@trasno.org>" # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * quintela/tags/migration/20170517: migration: Move check_migratable() into qdev.c migration: Move postcopy stuff to postcopy-ram.c migration: Move page_cache.c to migration/ migration: Create migration/blocker.h ram: Rename RAM_SAVE_FLAG_COMPRESS to RAM_SAVE_FLAG_ZERO migration: Pass Error ** argument to {save,load}_vmstate migration: Fix regression with compression threads Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-05-17qdev: Replace cannot_instantiate_with_device_add_yet with !user_creatableEduardo Habkost
cannot_instantiate_with_device_add_yet was introduced by commit efec3dd631d94160288392721a5f9c39e50fb2bc to replace no_user. It was supposed to be a temporary measure. When it was introduced, we had 54 cannot_instantiate_with_device_add_yet=true lines in the code. Today (3 years later) this number has not shrunk: we now have 57 cannot_instantiate_with_device_add_yet=true lines. I think it is safe to say it is not a temporary measure, and we won't see the flag go away soon. Instead of a long field name that misleads people to believe it is temporary, replace it a shorter and less misleading field: user_creatable. Except for code comments, changes were generated using the following Coccinelle patch: @@ expression DC; @@ ( -DC->cannot_instantiate_with_device_add_yet = false; +DC->user_creatable = true; | -DC->cannot_instantiate_with_device_add_yet = true; +DC->user_creatable = false; ) @@ typedef ObjectClass; expression dc; identifier class, data; @@ static void device_class_init(ObjectClass *class, void *data) { ... dc->hotpluggable = true; +dc->user_creatable = true; ... } @@ @@ struct DeviceClass { ... -bool cannot_instantiate_with_device_add_yet; +bool user_creatable; ... } @@ expression DC; @@ ( -!DC->cannot_instantiate_with_device_add_yet +DC->user_creatable | -DC->cannot_instantiate_with_device_add_yet +!DC->user_creatable ) Cc: Alistair Francis <alistair.francis@xilinx.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Thomas Huth <thuth@redhat.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: Marcel Apfelbaum <marcel@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170503203604.31462-2-ehabkost@redhat.com> [ehabkost: kept "TODO remove once we're there" comment] Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-05-17migration: Create migration/blocker.hJuan Quintela
This allows us to remove lots of includes of migration/migration.h Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-05-16Merge remote-tracking branch 'aurel32/tags/pull-target-sh4-20170513' into ↵Stefan Hajnoczi
staging Queued target/sh4 patches # gpg: Signature made Sat 13 May 2017 10:25:41 AM BST # gpg: using RSA key 0xBA9C78061DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * aurel32/tags/pull-target-sh4-20170513: target/sh4: use cpu_loop_exit_restore target/sh4: trap unaligned accesses target/sh4: movua.l is an SH4-A only instruction target/sh4: implement tas.b using atomic helper target/sh4: generate fences for SH4 target/sh4: optimize gen_write_sr using extract op target/sh4: optimize gen_store_fpr64 target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump target/sh4: only save flags state at the end of the TB target/sh4: fix BS_EXCP exit target/sh4: fix BS_STOP exit target/sh4: move DELAY_SLOT_TRUE flag into a separate global target/sh4: do not include DELAY_SLOT_TRUE in the TB state target/sh4: get rid of DELAY_SLOT_CLEARME target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-05-16Merge remote-tracking branch 'rth/tags/pull-s390-20170512' into stagingStefan Hajnoczi
Queued target/s390 patches # gpg: Signature made Sat 13 May 2017 12:33:08 AM BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * rth/tags/pull-s390-20170512: target/s390x: implement serialization in BRANCH CONDITION target/s390x: fix SIGNAL PROCESSOR return value target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK target/s390x: Use atomic operations for LOAD AND OP target/s390x: Use atomic operations for COMPARE SWAP target/s390x: Implement LOAD PAIR DISJOINT target/s390x: Diagnose specification exception for atomics target/s390x: Implement LOAD PROGRAM PARAMETER target/s390x: Implement STORE FACILITIES LIST EXTENDED Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-14 03:16:12 +0000