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2019-05-28target/mips: convert UHI_plog to use common semihosting codeAlex Bennée
Rather than printing directly to stdout lets use our common semihosting code. There is one minor difference in that the output currently defaults to stderr instead of stdout however this can be controlled by connecting semihosting to a chardev. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-05-28target/mips: only build mips-semi for softmmuAlex Bennée
The is_uhi gates all semihosting calls and always returns false for CONFIG_USER_ONLY builds. There is no reason to build and link mips-semi for these builds so lets fix that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28target/arm: correct return values for WRITE/READ in arm-semiAlex Bennée
The documentation says the write should return the number of bytes not written on an error (0 means everything was written). Read provides a buffer length and the return value should be the buffer length - bytes actually read. Remove the incorrect FIXME's and return the correct values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-05-28target/arm: add LOG_UNIMP messages to arm-semiAlex Bennée
Clean-up our unimplemented bits with a proper message. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28target/arm: use the common interface for WRITE0/WRITEC in arm-semiAlex Bennée
Now we have a common semihosting console interface use that for our string output. However ARM is currently unique in also supporting semihosting for linux-user so we need to replicate the API in linux-user. If other architectures gain this support we can move the file later. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28target/arm: fixup some of the commentary for arm-semiAlex Bennée
This cleans up a number of the block comments to fit the proper style. While we are at it we also reference the official specification and document what the return register value can be. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-05-28semihosting: move semihosting configuration into its own directoryAlex Bennée
In preparation for having some more common semihosting code let's excise the current config magic from vl.c into its own file. We shall later add more conditionals to the build configurations so we can avoid building this if we don't need it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-26target/mips: realign comments to fix checkpatch warningsJules Irenge
Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>
2019-05-26target/mips: add or remove space to fix checkpatch errorsJules Irenge
Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around that..." "ERROR: space required after that..." "ERROR: space required before the open parenthesis" "ERROR: space required after that..." "ERROR: space prohibited between function name and open parenthesis" "ERROR: code indent should never use tabs" "ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com>
2019-05-26mips: Decide to map PAGE_EXEC in map_addressJakub Jermář
This commit addresses QEMU Bug #1825311: mips_cpu_handle_mmu_fault renders all accessed pages executable It allows finer-grained control over whether the accessed page should be executable by moving the decision to the underlying map_address function, which has more information for this. As a result, pages that have the XI bit set in the TLB and are accessed for read/write, don't suddenly end up being executable. Fixes: https://bugs.launchpad.net/qemu/+bug/1825311 Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry') Signed-off-by: Jakub Jermář <jakub.jermar@kernkonzept.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com>
2019-05-26target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic
The old version of the helper for the INSERT.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic
The old version of the helper for the COPY_U.<B|H|W> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic
The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic
Fix the case when the host is a big endian machine, and change the approach toward ST.<B|H|W|D> instruction helpers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic
Fix the case when the host is a big endian machine, and change the approach toward LD.<B|H|W|D> instruction helpers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic
MSA instructions MOD_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 255, 256). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554207110-9113-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic
MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 141, 142). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554207110-9113-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens
There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip register are read-only." Further, if an interrupt is not delegated to mode x, then "the corresponding bits in xip [...] should appear to be hardwired to zero. This patch implements both of those requirements. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add checks for several RVC reserved operandsRichard Henderson
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis
Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Revieweb-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Improve the scause logicAlistair Francis
No functional change, just making the code easier to read. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis
The requirement of holding the iothread_mutex is burdersome when swapping the background and foreground registers in the Hypervisor extension. To avoid the requrirement let's set the interrupt asynchronously. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis
At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Remove spaces from register namesRichard Henderson
These extra spaces make the "-d op" dump look weird. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson
The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson
This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Use pattern groups in insn16.decodeRichard Henderson
This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson
Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Merge argument sets for insn32 and insn16Richard Henderson
In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Use --static-decode for decodetreeRichard Henderson
The generated functions are only used within translate.c and do not need to be global, or declared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau
This patch introduces wrappers around the tcg_gen_exit_tb() and tcg_gen_lookup_and_goto_ptr() functions that handle single stepping, i.e. call gen_exception_debug() when single stepping is enabled. Theses functions are then used instead of the originals, bringing single stepping handling in places where it was previously ignored such as jalr and system branch instructions (ecall, mret, sret, etc.). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Do not allow sfence.vma from user modeJonathan Behrens
The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-23arm: Remove unnecessary includes of hw/arm/arm.hPeter Maydell
The hw/arm/arm.h header now only includes declarations relating to boot.c code, so it is only needed by Arm board or SoC code. Remove some unnecessary inclusions of it from target/arm files and from hw/intc/armv7m_nvic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
2019-05-23target/arm: Fix vector operation segfaultAlistair Francis
Commit 89e68b575 "target/arm: Use vector operations for saturation" causes this abort() when booting QEMU ARM with a Cortex-A15: 0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6 1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6 2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673 3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386 4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289 5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612 6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96 7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901 8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736 9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407 10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728 11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431 12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735 13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709 14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502 15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread. This patch ensures that we don't hit the abort() in the second switch case in disas_neon_data_insn() as we will return from the first case. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23target/arm: Simplify BFXIL expansionRichard Henderson
The mask implied by the extract is redundant with the one implied by the deposit. Also, fix spelling of BFXIL. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190514011129.11330-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23target/arm: Use extract2 for EXTRRichard Henderson
This is, after all, how we implement extract2 in tcg/aarch64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190514011129.11330-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-23Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into stagingPeter Maydell
Introduce qemu_guest_getrandom. Use qemu_guest_getrandom in aspeed, nrf51, bcm2835, exynos4210 rng devices. Use qemu_guest_getrandom in target/ppc darn instruction. Support ARMv8.5-RNG extension. Support x86 RDRAND extension. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Laurent Vivier <laurent@vivier.eu> # gpg: Signature made Wed 22 May 2019 19:36:43 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-rng-20190522: (25 commits) target/i386: Implement CPUID_EXT_RDRAND target/ppc: Use qemu_guest_getrandom for DARN target/ppc: Use gen_io_start/end around DARN target/arm: Implement ARMv8.5-RNG target/arm: Put all PAC keys into a structure hw/misc/exynos4210_rng: Use qemu_guest_getrandom hw/misc/bcm2835_rng: Use qemu_guest_getrandom_nofail hw/misc/nrf51_rng: Use qemu_guest_getrandom_nofail aspeed/scu: Use qemu_guest_getrandom_nofail linux-user: Remove srand call linux-user/aarch64: Use qemu_guest_getrandom for PAUTH keys linux-user: Use qemu_guest_getrandom_nofail for AT_RANDOM linux-user: Call qcrypto_init if not using -seed linux-user: Initialize pseudo-random seeds for all guest cpus cpus: Initialize pseudo-random seeds for all guest cpus util: Add qemu_guest_getrandom and associated routines ui/vnc: Use gcrypto_random_bytes for start_auth_vnc ui/vnc: Split out authentication_failed crypto: Change the qcrypto_random_bytes buffer type to void* crypto: Use getrandom for qcrypto_random_bytes ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-22target/i386: Implement CPUID_EXT_RDRANDRichard Henderson
We now have an interface for guest visible random numbers. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-22target/ppc: Use qemu_guest_getrandom for DARNRichard Henderson
We now have an interface for guest visible random numbers. Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-22target/ppc: Use gen_io_start/end around DARNRichard Henderson
Generating a random number counts as I/O, as it cannot be replayed and produce the same results. Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-22target/arm: Implement ARMv8.5-RNGRichard Henderson
Use the newly introduced infrastructure for guest random numbers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-22target/arm: Put all PAC keys into a structureRichard Henderson
This allows us to use a single syscall to initialize them all. Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-18 08:20:38 +0000