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2019-06-07s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand
Similar to VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand
The only FP instruction we can implement without an helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand
Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand
We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand
Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand
We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand
We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand
1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand
Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand
As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand
1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()David Hildenbrand
Vector floating-point instructions will require these functions, so allow to use them from other files. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Introduce tcg_s390_vector_exception()David Hildenbrand
Handling is similar to data exceptions, however we can always store the VXC into the lowore and the FPC: z14 PoP, 6-20, "Vector-Exception Code" When a vector-processing exception causes a pro- gram interruption, a vector-exception code (VXC) is stored at location 147, and zeros are stored at loca- tions 144-146. The VXC is also placed in the DXC field of the floating-point-control (FPC) register if bit 45 of control register 0 is one. When bit 45 of control register 0 is zero and bit 46 of control register 0 is one, the DXC field of the FPC register and the con- tents of storage at location 147 are unpredictable. Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Store only the necessary amount of doublewords for STFLEDavid Hildenbrand
The PoP (z14, 7-382) says: Doublewords to the right of the doubleword in which the highest-numbered facility bit is assigned for a model may or may not be stored. However, stack protection in certain binaries can't deal with that. "gzip" example code: f1b4: a7 08 00 03 lhi %r0,3 f1b8: b2 b0 f0 a0 stfle 160(%r15) f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15) f1c2: c0 2b 00 00 00 01 nilf %r2,1 f1c8: b2 4f 00 10 ear %r1,%a0 f1cc: b9 14 00 22 lgfr %r2,%r2 f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32 f1d6: b2 4f 00 11 ear %r1,%a1 f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1) f1e0: a7 74 00 06 jne f1ec <file_read@@Base+0x1bc> f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15) f1ea: 07 fe br %r14 f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt> In QEMU, we currently have: max_bytes = 24 the code asks for (3 + 1) doublewords == 32 bytes. If we write 32 bytes instead of only 24, and return "2 + 1" doublewords ("one less than the number of doulewords needed to contain all of the facility bits"), the example code detects a stack corruption. In my opinion, the code is wrong. However, it seems to work fine on real machines. So let's limit storing to the minimum of the requested and the maximum doublewords. Cc: Stefan Liebler <stli@linux.ibm.com> Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Fix max_byte detection for stfleDavid Hildenbrand
used_stfl_bytes is 0, before initialized via prepare_stfl() on the first invocation. We have to move the calculation of max_bytes after prepare_stfl(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Use uint64_t for vector registersDavid Hildenbrand
CPU_DoubleU is primarily used to reinterpret between integer and floats. We don't really need this functionality. So let's just keep it simple and use an uint64_t. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Align vector registers to 16 bytesDavid Hildenbrand
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store") revealed that the vregs are not aligned to 16 bytes. Align them to 16 bytes, to avoid segfault'ing on x86. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand
Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand
Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand
Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand
Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07target/mips: Unroll loops in helpers for MSA logic instructionsAleksandar Markovic
Unroll loops in helpers for MSA logic instructions for better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07target/mips: Outline places for future MSA helpersAleksandar Markovic
Outline places for future MSA helpers to follow the same organization as in MSA tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-06target/mips: Fix block-comment-related issues in msa_helper.cAleksandar Markovic
Fix block-comment-related issues reported by checkpatch for file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-06target/mips: Fix space-related format issues in msa_helper.cAleksandar Markovic
Fix space-related format issues reported by checkpatch in file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-03i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitorWanpeng Li
The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR IA32_MISC_ENABLE MWAIT bit and as userspace has control of them both, it is userspace's job to configure both bits to match on the initial setup. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1557813999-9175-1-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-01target/mips: Improve performance of certain MSA instructionsMateja Marjanovic
Eliminate loops for better performance. Following MSA instructions from "UNOP" group are affected: - NLZC.<B|H|W|D> - NLOC.<B|H|W|D> - PCNT.<B|H|W|D> Following MSA instructions from "BINOP" group are affected: - ADD_A.<B|H|W|D> - ADDS_A.<B|H|W|D> - ADDS_S.<B|H|W|D> - ADDS_U.<B|H|W|D> - ADDV.<B|H|W|D> - ASUB_S.<B|H|W|D> - ASUB_U.<B|H|W|D> - AVE_S.<B|H|W|D> - AVE_U.<B|H|W|D> - AVER_S.<B|H|W|D> - AVER_U.<B|H|W|D> - BCLR.<B|H|W|D> - BNEG.<B|H|W|D> - BSET.<B|H|W|D> - CEQ.<B|H|W|D> - CLE_S.<B|H|W|D> - CLE_U.<B|H|W|D> - CLT_S.<B|H|W|D> - CLT_U.<B|H|W|D> - DIV_S.<B|H|W|D> - DIV_U.<B|H|W|D> - DOTP_S.<B|H|W|D> - DOTP_U.<B|H|W|D> - HADD_S.<B|H|W|D> - HADD_U.<B|H|W|D> - HSUB_S.<B|H|W|D> - HSUB_U.<B|H|W|D> - MAX_A.<B|H|W|D> - MAX_S.<B|H|W|D> - MAX_U.<B|H|W|D> - MIN_A.<B|H|W|D> - MIN_S.<B|H|W|D> - MIN_U.<B|H|W|D> - MOD_S.<B|H|W|D> - MOD_U.<B|H|W|D> - MUL_Q.<B|H|W|D> - MULR_Q.<B|H|W|D> - MULV.<B|H|W|D> - SLL.<B|H|W|D> - SRA.<B|H|W|D> - SRAR.<B|H|W|D> - SRL.<B|H|W|D> - SRLR.<B|H|W|D> - SUBS_S.<B|H|W|D> - SUBS_U.<B|H|W|D> - SUBSUS_U.<B|H|W|D> - SUBSUU_S.<B|H|W|D> - SUBV.<B|H|W|D> Following MSA instructions from "TEROP" group are affected: - BINSL.<B|H|W|D> - BINSR.<B|H|W|D> - DPADD_S.<B|H|W|D> - DPADD_U.<B|H|W|D> - DPSUB_S.<B|H|W|D> - DPSUB_U.<B|H|W|D> - MADD_Q.<B|H|W|D> - MADDR_Q.<B|H|W|D> - MADDV.<B|H|W|D> - MSUB_Q.<B|H|W|D> - MSUBR_Q.<B|H|W|D> - MSUBV.<B|H|W|D> Additionally, following MSA instructionas are also affected: - ILVL.<B|H|W|D> - ILVR.<B|H|W|D> - ILVEV.<B|H|W|D> - ILVOD.<B|H|W|D> - PCKEV.<B|H|W|D> - PCKOD.<B|H|W|D> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1551718283-4487-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-06-01target/mips: Clean up lmi_helper.cAleksandar Markovic
Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1556018982-3715-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01target/mips: Clean up dsp_helper.cAleksandar Markovic
Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1556018982-3715-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01target/mips: Add emulation of MMI instruction PCPYUDMateja Marjanovic
Add emulation of MMI instruction PCPYUD. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-06-01target/mips: Add emulation of MMI instruction PCPYLDMateja Marjanovic
Add emulation of MMI instruction PCPYLD. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-06-01target/mips: Add emulation of MMI instruction PCPYHMateja Marjanovic
Add emulation of MMI instruction PCPYH. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-29spapr/xive: add KVM supportCédric Le Goater
This introduces a set of helpers when KVM is in use, which create the KVM XIVE device, initialize the interrupt sources at a KVM level and connect the interrupt presenters to the vCPU. They also handle the initialization of the TIMA and the source ESB memory regions of the controller. These have a different type under KVM. They are 'ram device' memory mappings, similarly to VFIO, exposed to the guest and the associated VMAs on the host are populated dynamically with the appropriate pages using a fault handler. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190513084245.25755-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Use vector variable shifts for VSL, VSR, VSRARichard Henderson
The gvec expanders take care of masking the shift amount against the element width. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190518191430.21686-2-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]pAnton Blanchard
We were using set_cpu_vsr*() when we should have used get_cpu_vsr*(). Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190509104912.6b754dff@kryten> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STOREAnton Blanchard
A few small optimisations: In VSX_LOAD_SCALAR_DS() we can don't need to read the VSR via get_cpu_vsrh(). Split VSX_VECTOR_LOAD_STORE() into two functions. Loads only need to write the VSRs (set_cpu_vsr*()) and stores only need to read the VSRs (get_cpu_vsr*()) Thanks to Mark Cave-Ayland for the suggestions. Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190509103545.4a7fa71a@kryten> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Fix xxspltibAnton Blanchard
xxspltib raises a VMX or a VSX exception depending on the register set it is operating on. We had a check, but it was backwards. Fixes: f113283525a4 ("target-ppc: add xxspltib instruction") Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190509061713.69490488@kryten> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Fix vsum2swsAnton Blanchard
A recent cleanup changed the pre zeroing of the result from 64 bit to 32 bit operations: - result.u64[i] = 0; + result.VsrW(i) = 0; This corrupts the result. Fixes: 60594fea298d ("target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in int_helper.c") Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190507004811.29968-9-anton@ozlabs.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Fix vslv and vsrvAnton Blanchard
vslv and vsrv are broken on little endian, we append 00 to the high byte not the low byte. Fix it by using the VsrB() accessor. Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190507004811.29968-6-anton@ozlabs.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Fix xxbrq, xxbrwAnton Blanchard
Fix a typo in xxbrq and xxbrw where we put both results into the lower doubleword. Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190507004811.29968-3-anton@ozlabs.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc: Fix xvxsigdpAnton Blanchard
Fix a typo in xvxsigdp where we put both results into the lower doubleword. Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()") Signed-off-by: Anton Blanchard <anton@ozlabs.org> Message-Id: <20190507004811.29968-1-anton@ozlabs.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29target/ppc/kvm: Fix trace typoBoxuan Li
Signed-off-by: Boxuan Li <liboxuan@connect.hku.hk> Message-Id: <20190430172842.27369-1-liboxuan@connect.hku.hk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-28Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-next-280519-2' into staging Various testing updates - semihosting re-factor (used in system tests) - aarch64 and alpha system tests - editorconfig tweak for .S - some docker image updates - iotests clean-up (without make check inclusion) # gpg: Signature made Tue 28 May 2019 17:26:34 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-next-280519-2: (27 commits) tests/qemu-iotests: re-format output to for make check-block tests/qemu-iotests/group: Re-use the "auto" group for tests that can always run Makefile.target: support per-target coverage reports Makefile: include per-target build directories in coverage report Makefile: fix coverage-report reference to BUILD_DIR .travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests tests/tcg/alpha: add system boot.S tests/tcg/multiarch: expand system memory test to cover more tests/tcg/minilib: support %c format char tests/tcg/multiarch: move the system memory test tests/tcg/aarch64: add system boot.S editorconfig: add settings for .s/.S files tests/tcg/multiarch: add hello world system test tests/tcg/multiarch: add support for multiarch system tests tests/docker: Test more components on the Fedora default image tests/docker: add ubuntu 18.04 MAINTAINERS: update for semihostings new home target/mips: convert UHI_plog to use common semihosting code target/mips: only build mips-semi for softmmu target/arm: correct return values for WRITE/READ in arm-semi ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-28Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-may-19-2019-v3' into staging MIPS queue for May 19th, 2019 - v3 # gpg: Signature made Sun 26 May 2019 17:07:07 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-may-19-2019-v3: BootLinuxSshTest: Test some userspace commands on Malta target/mips: realign comments to fix checkpatch warnings target/mips: add or remove space to fix checkpatch errors linux-user: fix __NR_semtimedop undeclared error mips: Decide to map PAGE_EXEC in map_address target/mips: Refactor and fix INSERT.<B|H|W|D> instructions target/mips: Refactor and fix COPY_U.<B|H|W> instructions target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-18 03:17:49 +0000