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2019-09-05target/arm: Convert RFE and SRSRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert SVCRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert B, BL, BLX (immediate)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Diagnose base == pc for LDM/STMRichard Henderson
We have been using store_reg and not store_reg_for_load when writing back a loaded value into the base register. At first glance this is incorrect when base == pc, however that case is UNPREDICTABLE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Diagnose too few registers in list for LDM/STMRichard Henderson
This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Diagnose writeback register in list for LDM for v7Richard Henderson
Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN value back to the base register. Starting in v7 this is UNPREDICTABLE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert LDM, STMRichard Henderson
This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert MOVW, MOVTRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Signed multiply, signed and unsigned divideRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert packing, unpacking, saturation, and reversalRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Parallel addition and subtractionRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDFRichard Henderson
In op_bfx, note that tcg_gen_{,s}extract_i32 already checks for width == 32, so we don't need to special case that here. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Diagnose UNPREDICTABLE ldrex/strex casesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Synchronization primitivesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert load/store (register, immediate, literal)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert T32 ADDW/SUBWRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert the rest of A32 Miscelaneous instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert ERETRichard Henderson
Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert CLZRichard Henderson
Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert BX, BXJ, BLX (register)Richard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Cyclic Redundancy CheckRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert MRS/MSR (banked, register)Richard Henderson
The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert MSR (immediate) and hintsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Simplify op_smlawx for SMLAW*Richard Henderson
By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Simplify op_smlaxxx for SMLAL*Richard Henderson
Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Halfword multiply and multiply accumulateRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Saturating addition and subtractionRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Simplify UMAALRichard Henderson
Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert multiply and multiply accumulateRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Data Processing (immediate)Richard Henderson
Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Data Processing (reg-shifted-reg)Richard Henderson
Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Convert Data Processing (register)Richard Henderson
Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Add stubs for aa32 decodetreeRichard Henderson
Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-05target/arm: Use store_reg_from_load in thumb2 codeRichard Henderson
This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn == 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04target/openrisc: Update cpu "any" to v1.3Richard Henderson
Now that the two updates from v1.3 are implemented, update the "any" cpu to enable it. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Implement l.adrpRichard Henderson
This was added to the 1.3 spec. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Implement move to/from FPCSRRichard Henderson
Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson
These were added to the 1.3 spec. For OF32S, validate AVR. But OF64A32 is itself new to 1.3 so no extra check needed. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson
This is hardware support for double-precision floating-point using pairs of 32-bit registers. Fix latent bugs in the heretofore unused helper_itofd and helper_ftoid. Include the bit for cpu "any". Change the default cpu for linux-user to "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson
Make sure the OF32S insns are enabled before allowing execution. Include the missing bit for cpu "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Fix lf.ftoi.sRichard Henderson
The specification of this insn is round-to-zero. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Add VR2 and AVR special processor registersRichard Henderson
Update the CPUCFG bits to arch v1.3. Include support for AVRP for cpu "any". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson
These registers are read-only and implementation specific. Initiailize VR for the first time; take the OR1200 values from the verilog source. Note that moving fields within CPUOpenRISCState does not affect migration. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Make VR and PPC read-onlyRichard Henderson
These SPRs are read-only. The writes can simply be ignored, as we already do for other read-only (or missing) registers. There is no reason to mask the value in env->vr. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson
Finish the race condition fix from the previous patch. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson
The writes to cpu_R[0] are now a race across threads, now that we do code generation in parallel. Stage the change by introducing a function to return the temp for R0. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson
We will need this context in the next patch. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190903' into stagingPeter Maydell
Allow page table bit to swap endianness. Reorganize watchpoints out of i/o path. Return host address from probe_write / probe_access. # gpg: Signature made Tue 03 Sep 2019 16:47:50 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190903: (36 commits) tcg: Factor out probe_write() logic into probe_access() tcg: Make probe_write() return a pointer to the host page s390x/tcg: Pass a size to probe_write() in do_csst() hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well tcg: Enforce single page access in probe_write() tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code s390x/tcg: Fix length calculation in probe_write_access() s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in probe_write_access() tcg: Check for watchpoints in probe_write() cputlb: Handle watchpoints via TLB_WATCHPOINT cputlb: Remove double-alignment in store_helper cputlb: Fix size operand for tlb_fill on unaligned store exec: Factor out cpu_watchpoint_address_matches cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK exec: Factor out core logic of check_watchpoint() exec: Move user-only watchpoint stubs inline target/sparc: sun4u Invert Endian TTE bit target/sparc: Add TLB entry with attributes cputlb: Byte swap memory transaction attribute ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190903' into staging target-arm queue: * Revert and correctly fix refactoring of unallocated_encoding() * Take exceptions on ATS instructions when needed * aspeed/timer: Provide back-pressure information for short periods * memory: Remove unused memory_region_iommu_replay_all() * hw/arm/smmuv3: Log a guest error when decoding an invalid STE * hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations * target/arm: Fix SMMLS argument order * hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate * hw/arm: Correct reference counting for creation of various objects * includes: remove stale [smp|max]_cpus externs * tcg/README: fix typo * atomic_template: fix indentation in GEN_ATOMIC_HELPER * include/exec/cpu-defs.h: fix typo * target/arm: Free TCG temps in trans_VMOV_64_sp() * target/arm: Don't abort on M-profile exception return in linux-user mode # gpg: Signature made Tue 03 Sep 2019 16:35:19 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190903: (21 commits) target/arm: Don't abort on M-profile exception return in linux-user mode target/arm: Free TCG temps in trans_VMOV_64_sp() include/exec/cpu-defs.h: fix typo atomic_template: fix indentation in GEN_ATOMIC_HELPER tcg/README: fix typo s/afterwise/afterwards/ includes: remove stale [smp|max]_cpus externs hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting hw/arm/fsl-imx: Add the cpu as child of the SoC object hw/arm: Use sysbus_init_child_obj for correct reference counting hw/arm: Use object_initialize_child for correct reference counting hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate target/arm: Fix SMMLS argument order hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations hw/arm/smmuv3: Log a guest error when decoding an invalid STE memory: Remove unused memory_region_iommu_replay_all() aspeed/timer: Provide back-pressure information for short periods target/arm: Take exceptions on ATS instructions when needed target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions target/arm: Factor out unallocated_encoding for aarch32 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-29-2019' ↵Peter Maydell
into staging MIPS queue for August 29th, 2019 # gpg: Signature made Thu 29 Aug 2019 11:19:28 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-29-2019: (31 commits) target/mips: Fix emulation of ST.W in system mode target/mips: Clean up handling of CP0 register 31 target/mips: Clean up handling of CP0 register 30 target/mips: Clean up handling of CP0 register 29 target/mips: Clean up handling of CP0 register 28 target/mips: Clean up handling of CP0 register 27 target/mips: Clean up handling of CP0 register 26 target/mips: Clean up handling of CP0 register 25 target/mips: Clean up handling of CP0 register 24 target/mips: Clean up handling of CP0 register 23 target/mips: Clean up handling of CP0 register 20 target/mips: Clean up handling of CP0 register 19 target/mips: Clean up handling of CP0 register 18 target/mips: Clean up handling of CP0 register 17 target/mips: Clean up handling of CP0 register 16 target/mips: Clean up handling of CP0 register 15 target/mips: Clean up handling of CP0 register 14 target/mips: Clean up handling of CP0 register 13 target/mips: Clean up handling of CP0 register 12 target/mips: Clean up handling of CP0 register 11 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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