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AgeCommit message (Expand)Author
2019-09-05target/arm: Convert RFE and SRSRichard Henderson
2019-09-05target/arm: Convert SVCRichard Henderson
2019-09-05target/arm: Convert B, BL, BLX (immediate)Richard Henderson
2019-09-05target/arm: Diagnose base == pc for LDM/STMRichard Henderson
2019-09-05target/arm: Diagnose too few registers in list for LDM/STMRichard Henderson
2019-09-05target/arm: Diagnose writeback register in list for LDM for v7Richard Henderson
2019-09-05target/arm: Convert LDM, STMRichard Henderson
2019-09-05target/arm: Convert MOVW, MOVTRichard Henderson
2019-09-05target/arm: Convert Signed multiply, signed and unsigned divideRichard Henderson
2019-09-05target/arm: Convert packing, unpacking, saturation, and reversalRichard Henderson
2019-09-05target/arm: Convert Parallel addition and subtractionRichard Henderson
2019-09-05target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDFRichard Henderson
2019-09-05target/arm: Diagnose UNPREDICTABLE ldrex/strex casesRichard Henderson
2019-09-05target/arm: Convert Synchronization primitivesRichard Henderson
2019-09-05target/arm: Convert load/store (register, immediate, literal)Richard Henderson
2019-09-05target/arm: Convert T32 ADDW/SUBWRichard Henderson
2019-09-05target/arm: Convert the rest of A32 Miscelaneous instructionsRichard Henderson
2019-09-05target/arm: Convert ERETRichard Henderson
2019-09-05target/arm: Convert CLZRichard Henderson
2019-09-05target/arm: Convert BX, BXJ, BLX (register)Richard Henderson
2019-09-05target/arm: Convert Cyclic Redundancy CheckRichard Henderson
2019-09-05target/arm: Convert MRS/MSR (banked, register)Richard Henderson
2019-09-05target/arm: Convert MSR (immediate) and hintsRichard Henderson
2019-09-05target/arm: Simplify op_smlawx for SMLAW*Richard Henderson
2019-09-05target/arm: Simplify op_smlaxxx for SMLAL*Richard Henderson
2019-09-05target/arm: Convert Halfword multiply and multiply accumulateRichard Henderson
2019-09-05target/arm: Convert Saturating addition and subtractionRichard Henderson
2019-09-05target/arm: Simplify UMAALRichard Henderson
2019-09-05target/arm: Convert multiply and multiply accumulateRichard Henderson
2019-09-05target/arm: Convert Data Processing (immediate)Richard Henderson
2019-09-05target/arm: Convert Data Processing (reg-shifted-reg)Richard Henderson
2019-09-05target/arm: Convert Data Processing (register)Richard Henderson
2019-09-05target/arm: Add stubs for aa32 decodetreeRichard Henderson
2019-09-05target/arm: Use store_reg_from_load in thumb2 codeRichard Henderson
2019-09-04target/openrisc: Update cpu "any" to v1.3Richard Henderson
2019-09-04target/openrisc: Implement l.adrpRichard Henderson
2019-09-04target/openrisc: Implement move to/from FPCSRRichard Henderson
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson
2019-09-04target/openrisc: Fix lf.ftoi.sRichard Henderson
2019-09-04target/openrisc: Add VR2 and AVR special processor registersRichard Henderson
2019-09-04target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson
2019-09-04target/openrisc: Make VR and PPC read-onlyRichard Henderson
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson
2019-09-04Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190903' into stagingPeter Maydell
2019-09-04Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190903'...Peter Maydell
2019-09-04Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-29-2019' ...Peter Maydell