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2019-05-16target/m68k: In get_physical_address() check for memory access failuresPeter Maydell
In get_physical_address(), use address_space_ldl() and address_space_stl() instead of ldl_phys() and stl_phys(). This allows us to check whether the memory access failed. For the moment, we simply return -1 in this case; add a TODO comment that we should ideally generate the appropriate kind of fault. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20181210165636.28366-3-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-05-16target/m68k: In dump_address_map() check for memory access failuresPeter Maydell
In dump_address_map(), use address_space_ldl() instead of ldl_phys(). This allows us to check whether the memory access failed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20181210165636.28366-2-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-05-16Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into stagingPeter Maydell
Add CPUClass::tlb_fill. Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. # gpg: Signature made Fri 10 May 2019 19:48:37 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190510: (27 commits) tcg: Use tlb_fill probe from tlb_vaddr_to_host tcg: Remove CPUClass::handle_mmu_fault tcg: Use CPUClass::tlb_fill in cputlb.c target/xtensa: Convert to CPUClass::tlb_fill target/unicore32: Convert to CPUClass::tlb_fill target/tricore: Convert to CPUClass::tlb_fill target/tilegx: Convert to CPUClass::tlb_fill target/sparc: Convert to CPUClass::tlb_fill target/sh4: Convert to CPUClass::tlb_fill target/s390x: Convert to CPUClass::tlb_fill target/riscv: Convert to CPUClass::tlb_fill target/ppc: Convert to CPUClass::tlb_fill target/openrisc: Convert to CPUClass::tlb_fill target/nios2: Convert to CPUClass::tlb_fill target/moxie: Convert to CPUClass::tlb_fill target/mips: Convert to CPUClass::tlb_fill target/mips: Tidy control flow in mips_cpu_handle_mmu_fault target/mips: Pass a valid error to raise_mmu_exception for user-only target/microblaze: Convert to CPUClass::tlb_fill target/m68k: Convert to CPUClass::tlb_fill ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-15target/xtensa: implement exclusive access optionMax Filippov
The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-15target/xtensa: update list of exception causesMax Filippov
Add XEA2 exception cause codes defined in recent Xtensa ISA releases. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-15target/xtensa: implement block prefetch option opcodesMax Filippov
Block prefetch option adds a bunch of non-privileged opcodes that may be implemented as nops since QEMU doesn't model caches. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-14target/xtensa: implement DIWBUI.P opcodeMax Filippov
This is a recent addition to the set of data cache opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-13target/xtensa: Use tcg_gen_abs_i32Richard Henderson
Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/tricore: Use tcg_gen_abs_tlPhilippe Mathieu-Daudé
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190423102145.14812-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/s390x: Use tcg_gen_abs_i64Richard Henderson
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/ppc: Use tcg_gen_abs_tlRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/ppc: Use tcg_gen_abs_i32Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190423102145.14812-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/cris: Use tcg_gen_abs_tlRichard Henderson
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_absRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Add support for integer absolute valueRichard Henderson
Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13tcg: Specify optional vector requirements with a listRichard Henderson
Replace the single opcode in .opc with a null-terminated array in .opt_opc. We still require that all opcodes be used with the same .vece. Validate the contents of this list with CONFIG_DEBUG_TCG. All tcg_gen_*_vec functions will check any list active during .fniv expansion. Swap the active list in and out as we expand other opcodes, or take control away from the front-end function. Convert all existing vector aware front ends. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-13Clean up decorations and whitespace around header guardsMarkus Armbruster
Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-9-armbru@redhat.com>
2019-05-13Normalize header guard symbol definition.Markus Armbruster
We commonly define the header guard symbol without an explicit value. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-8-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-05-13Clean up ill-advised or unusual header guardsMarkus Armbruster
Leading underscores are ill-advised because such identifiers are reserved. Trailing underscores are merely ugly. Strip both. Our header guards commonly end in _H. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-7-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Changes to slirp/ dropped, as we're about to spin it off]
2019-05-13Clean up header guards that don't match their file nameMarkus Armbruster
Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-6-armbru@redhat.com> [Rebase to master: update include/hw/net/ne2000-isa.h]
2019-05-13target/xtensa: Clean up core-isa.h header guardsMarkus Armbruster
scripts/clean-header-guards.pl warns these headers use reserved identifier _XTENSA_CORE_CONFIGURATION_H as header guard symbol. It additionally warns the guard doesn't match the file name. Reuse of the same guard symbol in multiple headers is okay as long as they cannot be included together. Since we can avoid guard symbol reuse easily, do so: use the guard symbol scripts/clean-header-guards.pl picks, less the TARGET_ prefix. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-5-armbru@redhat.com>
2019-05-13Use #include "..." for our own headers, <...> for othersMarkus Armbruster
Also delete a few redundant #include. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-2-armbru@redhat.com>
2019-05-10target/xtensa: implement MPU optionMax Filippov
The Memory Protection Unit Option (MPU) is a combined instruction and data memory protection unit with more protection flexibility than the Region Protection Option or the Region Translation Option but without any translation capability. It does no demand paging and does not reference a memory-based page table. Add memory protection unit option, internal state, SRs and opcodes. Implement MPU entries dumping in dump_mmu. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-10target/xtensa: add parity/ECC option SRsMax Filippov
Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option. The implementation is trivial since we don't emulate parity/ECC yet. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-10target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov
IDMA and scatter/gather features introduced new IRQ types that overlay_tool.h need to initialize Xtensa configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-10target/xtensa: make internal MMU functions staticMax Filippov
Remove declarations of the internal mmu_helper functions from the cpu.h, make these functions static and shuffle them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-10target/xtensa: get rid of centralized SR propertiesMax Filippov
SR numbers are not unique: different Xtensa options may reuse SR number for different purposes. Introduce generic rsr/wsr functions and xsr template and use them instead of centralized SR access functions. Change prototypes of specific rsr/wsr functions to match XtensaOpcodeOp and use them instead of centralized SR access functions. Put xtensa option that introduces SR into the second opcode description parameter and use it to test for rsr/wsr/xsr opcode validity. Extract SR and UR names for the xtensa_cpu_dump_state from libisa. Merge SRs and URs in the dump. Register names of used SR/UR in init_libisa and use these names for TCG globals referencing these SR/UR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-10tcg: Use tlb_fill probe from tlb_vaddr_to_hostRichard Henderson
Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for AArch64 SVE we have an existing emulation bug wherein we would mark the first element of a no-fault vector load as faulted (within the FFR, not via exception) just because we did not have its address in the TLB. Now we can properly only mark it as faulted if there really is no valid, readable translation, while still not raising an exception. (Note that beyond the first element of the vector, the hardware may report a fault for any reason whatsoever; with at least one element loaded, forward progress is guaranteed.) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson
We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/xtensa: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/unicore32: Convert to CPUClass::tlb_fillRichard Henderson
Remove the user-only functions, as we no longer have a user-only config. Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/tricore: Convert to CPUClass::tlb_fillRichard Henderson
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/tilegx: Convert to CPUClass::tlb_fillRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/sparc: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Artyom Tarasenko <atar4qemu@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/sh4: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/s390x: Convert to CPUClass::tlb_fillRichard Henderson
Cc: qemu-s390x@nongnu.org Cc: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/riscv: Convert to CPUClass::tlb_fillRichard Henderson
Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Cc: qemu-riscv@nongnu.org Cc: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/ppc: Convert to CPUClass::tlb_fillRichard Henderson
Cc: qemu-ppc@nongnu.org Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/nios2: Convert to CPUClass::tlb_fillRichard Henderson
Remove the leftover debugging cpu_dump_state. Cc: Chris Wulff <crwulff@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/moxie: Convert to CPUClass::tlb_fillRichard Henderson
Remove the user-only functions, as we don't have a user-only config. Fix the unconditional call to tlb_set_page, even if the translation failed. Cc: Anthony Green <green@moxielogic.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/mips: Convert to CPUClass::tlb_fillRichard Henderson
Note that env->active_tc.PC is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from do_raise_exception_err. Cc: Aleksandar Markovic <amarkovic@wavecomp.com> Cc: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/mips: Tidy control flow in mips_cpu_handle_mmu_faultRichard Henderson
Since the only non-negative TLBRET_* value is TLBRET_MATCH, the subsequent test for ret < 0 is useless. Use early return to allow subsequent blocks to be unindented. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/mips: Pass a valid error to raise_mmu_exception for user-onlyRichard Henderson
At present we give ret = 0, or TLBRET_MATCH. This gets matched by the default case, which falls through to TLBRET_BADADDR. However, it makes more sense to use a proper value. All of the tlb-related exceptions are handled identically in cpu_loop.c, so TLBRET_BADADDR is as good as any other. Retain it. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/microblaze: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/m68k: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/lm32: Convert to CPUClass::tlb_fillRichard Henderson
Cc: Michael Walle <michael@walle.cc> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/i386: Convert to CPUClass::tlb_fillRichard Henderson
We do not support probing, but we do not need it yet either. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/hppa: Convert to CPUClass::tlb_fillRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/cris: Convert to CPUClass::tlb_fillRichard Henderson
Remove dumping of cpu state. Remove logging of PC, as that value is garbage until cpu_restore_state. Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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