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AgeCommit message (Expand)Author
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis
2020-02-27target/riscv: Remove the hret instructionAlistair Francis
2020-02-27target/riscv: Add hfence instructionsAlistair Francis
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée
2020-02-25Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEADPaolo Bonzini
2020-02-25target/i386: check for empty register in FXAMPaolo Bonzini
2020-02-21target/arm: Set MVFR0.FPSP for ARMv5 cpusRichard Henderson
2020-02-21target/arm: Use isar_feature_aa32_simd_r32 more placesRichard Henderson
2020-02-21target/arm: Rename isar_feature_aa32_simd_r32Richard Henderson
2020-02-21target/arm: Convert PMULL.8 to gvecRichard Henderson
2020-02-21target/arm: Convert PMULL.64 to gvecRichard Henderson
2020-02-21target/arm: Convert PMUL.8 to gvecRichard Henderson
2020-02-21target/arm: Vectorize USHL and SSHLRichard Henderson
2020-02-21target/arm: Correctly implement ACTLR2, HACTLR2Peter Maydell
2020-02-21target/arm: Use FIELD_EX32 for testing 32-bit fieldsPeter Maydell
2020-02-21target/arm: Use isar_feature function for testing AA32HPD featurePeter Maydell
2020-02-21target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell
2020-02-21target/arm: Correct handling of PMCR_EL0.LC bitPeter Maydell
2020-02-21target/arm: Correct definition of PMCRDPPeter Maydell
2020-02-21target/arm: Provide ARMv8.4-PMU in '-cpu max'Peter Maydell
2020-02-21target/arm: Implement ARMv8.4-PMU extensionPeter Maydell
2020-02-21target/arm: Implement ARMv8.1-PMU extensionPeter Maydell
2020-02-21target/arm: Read debug-related ID registers from KVMPeter Maydell
2020-02-21target/arm: Move DBGDIDR into ARMISARegistersPeter Maydell
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