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2019-02-28target/arm: Implement VFMAL and VFMSL for aarch32Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219222952.22183-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28target/arm: Implement FMLAL and FMLSL for aarch64Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219222952.22183-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28target/arm: Add helpers for FMLALRichard Henderson
Note that float16_to_float32 rightly squashes SNaN to QNaN. But of course pickNaNMulAdd, for ARM, selects SNaNs first. So we have to preserve SNaN long enough for the correct NaN to be selected. Thus float16_to_float32_by_bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219222952.22183-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"Peter Maydell
This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730, which introduces a regression running EDK2 guest firmware under KVM: error: kvm run failed Function not implemented PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000 X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710 X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756 X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0 X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0 X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0 X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2 X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010 X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0 X29=000000013e3d12a0 X30=000000013f5a2518 SP=000000013b7be0b0 PSTATE=404003c4 -Z-- EL1t with [ 3507.926571] kvm [35042]: load/store instruction decoding not implemented in the host dmesg. Revert the change for the moment until we can investigate the cause of the regression. Reported-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28target/arm: Gate "miscellaneous FP" insns by ID register fieldPeter Maydell
There is a set of VFP instructions which we implement in disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit. These were all first introduced in v8 for A-profile, but in M-profile they appeared in v7M. Gate them on the MVFR2 FPMisc field instead, and rename the function appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
2019-02-28target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructionsPeter Maydell
Instead of gating the A32/T32 FP16 conversion instructions on the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of looking at ID register bits. In this case MVFR1 fields FPHP and SIMDHP indicate the presence of these insns. This change doesn't alter behaviour for any of our CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
2019-02-28target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()Peter Maydell
Currently the Arm arm-powerctl.h APIs allow: * arm_set_cpu_on(), which powers on a CPU and sets its initial PC and other startup state * arm_reset_cpu(), which resets a CPU which is already on (and fails if the CPU is powered off) but there is no way to say "power on a CPU as if it had just come out of reset and don't do anything else to it". Add a new function arm_set_cpu_on_and_reset(), which does this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
2019-02-28target/arm/cpu: Allow init-svtor property to be set after realizePeter Maydell
Make the M-profile "init-svtor" property be settable after realize. This matches the hardware, where this is a config signal which is sampled on CPU reset and can thus be changed between one reset and another. To do this we have to change the API we use to add the property. (We will need this capability for the SSE-200.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
2019-02-27target/mips: Preparing for adding MMI instructionsMateja Marjanovic
Set up MMI code to be compiled only for TARGET_MIPS64. This is needed so that GPRs are 64 bit, and combined with MMI registers, they will form full 128 bit registers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551183797-13570-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-02-26target/ppc: Basic POWER9 bare-metal radix MMU supportBenjamin Herrenschmidt
No guest support yet Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-13-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Support for POWER9 native hashBenjamin Herrenschmidt
(Might need more patch splitting) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-12-clg@kaod.org> [dwg: Hack to fix compile with some earlier include tweaks of mine] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Rename PATB/PATBE -> PATEBenjamin Herrenschmidt
That "b" means "base address" and thus shouldn't be in the name of actual entries and related constants. This patch keeps the synthetic patb_entry field of the spapr virtual hypervisor unchanged until I figure out if that has an impact on the migration stream. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-11-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Flush the TLB locally when the LPIDR is writtenBenjamin Herrenschmidt
Our TCG TLB only tags whether it's a HV vs a guest access, so it must be flushed when the LPIDR is changed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-10-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Fix synchronization of mttcg with broadcast TLB flushesBenjamin Herrenschmidt
Let's use the generic helper tlb_flush_all_cpus_synced() instead of iterating the CPUs ourselves. We do lose the optimization of clearing the "other" CPUs "need flush" flags but this shouldn't be a problem in practice. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Add basic support for "new format" HPTE as found on POWER9Benjamin Herrenschmidt
POWER9 (arch v3) slightly changes the HPTE format. The B bits move from the first to the second half of the HPTE, and the AVPN/ARPN are slightly shorter. However, under SPAPR, the hypercalls still take the old format (and probably will for the foreseable future). The simplest way to support this is thus to convert the HPTEs from new to old format when reading them if the MMU model is v3 and there is no virtual hypervisor, leaving the rest of the code unchanged. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-8-clg@kaod.org> [dwg: Moved function to .c since there was no real need for it in the .h] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Fix ordering of hash MMU accessesBenjamin Herrenschmidt
With mttcg, we can have MMU lookups happening at the same time as the guest modifying the page tables. Since the HPTEs of the hash table MMU contains two words (or double worlds on 64-bit), we need to make sure we read them in the right order, with the correct memory barrier. Additionally, when using emulated SPAPR mode, the hypercalls writing to the hash table must also perform the udpates in the right order. Note: This part is still not entirely correct Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Fix #include guard in mmu-book3s-v3.hBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Re-enable RMLS on POWER9 for virtual hypervisorsBenjamin Herrenschmidt
Historically the 64-bit server MMU supports two way of configuring the guest "real mode" mapping: - The "RMA" with is a single chunk of physically contiguous memory remapped as guest real, and controlled by the RMLS field in the LPCR register and the RMOR register. - The "VRMA" which uses special PTEs inserted in the partition hash table by the hypervisor. POWER9 deprecates the former, which is reflected by the filtering done in ppc_store_lpcr() which effectively prevents setting of the RMLS field. However, when using fully emulated SPAPR machines, our qemu code currently only knows how to define the guest real mode memory using RMLS. Thus you cannot run a SPAPR machine anymore with a POWER9 CPU model today. This works around it with a quirk in ppc_store_lpcr() to continue allowing the RMLS field to be set when using a virtual hypervisor. Ultimately we will want to implement configuring a VRMA instead which will also be necessary if we want to migrate a SPAPR guest between TCG and KVM but this is a lot more work. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc/mmu: Use LPCR:HR to chose radix vs. hash translationBenjamin Herrenschmidt
Now that LPCR:HR is set properly for SPAPR, use it for deciding the translation type, which also works for bare metal Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc/spapr: Set LPCR:HR when using Radix modeBenjamin Herrenschmidt
The HW relies on LPCR:HR along with the PATE to determine whether to use Radix or Hash mode. In fact it uses LPCR:HR more commonly than the PATE. For us, it's also more efficient to do so, especially since unlike the HW we do not maintain a cache of the current PATE and HV PATE in a generic place. Prepare the grounds for that by ensuring that LPCR:HR is set properly on SPAPR machines. Another option would have been to use a callback to get the PATE but this gets messy when implementing bare metal support, it's much simpler (and faster) to use LPCR. Since existing migration streams may not have it, fix it up in spapr_post_load() as well based on the pseudo-PATE entry that we keep. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215170029.15641-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Add support for LPCR:HEIC on POWER9Benjamin Herrenschmidt
This controls whether the External Interrupt (0x500) can be delivered to the hypervisor or not. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-11-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Add POWER9 external interrupt modelBenjamin Herrenschmidt
Adds support for the Hypervisor directed interrupts in addition to the OS ones. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: - modified the icp_realize() and xive_tctx_realize() to take into account explicitely the POWER9 interrupt model - introduced a specific power9_set_irq for POWER9 ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215161648.9600-10-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Add Hypervisor Virtualization Interrupt on POWER9Benjamin Herrenschmidt
This adds support for delivering that exception Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Detect erroneous condition in interrupt deliveryBenjamin Herrenschmidt
It's very easy for the CPU specific has_work() implementation and the logic in ppc_hw_interrupt() to be subtly out of sync. This can occasionally allow a CPU to wakeup from a PM state and resume executing past the PM instruction when it should resume at the 0x100 vector. This detects if it happens and aborts, making it a lot easier to catch such bugs when testing rather than chasing obscure guest misbehaviour. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Add POWER9 exception modelBenjamin Herrenschmidt
And use it to get the correct HILE bit in HID0 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Rename "in_pm_state" to "resume_as_sreset"Benjamin Herrenschmidt
To better reflect what this does, as it's specific to some of the P7/P8/P9 PM states, not generic. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Move "wakeup reset" code to a separate functionBenjamin Herrenschmidt
This moves the code to handle waking up from the 0x100 vector from powerpc_excp() to a separate function, as the former is already way too big as it is. No functional change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Fix support for "STOP light" states on POWER9Benjamin Herrenschmidt
STOP must act differently based on PSSCR:EC on POWER9. When set, it acts like the P7/P8 power management instructions and wake up at 0x100 based on the wakeup conditions in LPCR. When PSSCR:EC is clear however it will wakeup at the next instruction after STOP (if EE is clear) or take the corresponding interrupts (if EE is set). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Don't clobber MSR:EE on PM instructionsBenjamin Herrenschmidt
When issuing a power management instruction, we set MSR:EE to force ppc_hw_interrupt() into calling powerpc_excp() to deal with the fact that on P7 and P8, the system reset caused by the wakeup needs to be generated regardless of the MSR:EE value (using LPCR only). This however means that the OS will see a bogus SRR1:EE value which is a problem. It also prevents properly implementing P9 STOP "light". So fix this by instead putting some logic in ppc_hw_interrupt() to decide whether to deliver or not by taking into account the fact that we are waking up from sleep. The LPCR isn't checked as this is done in the has_work() test. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190215161648.9600-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-26target/ppc: Fix nip on power management instructionsBenjamin Herrenschmidt
Those instructions currently raise an exception from within the helper. This tends to result in a bogus nip value in the env context (typically the beginning of the TB). Such a helper needs a gen_update_nip() first. This fixes it with a different approach which is to throw the exception from translate.c instead of the helper using gen_exception_nip() which does the right thing. Exception EXCP_HLT is also used instead of POWERPC_EXCP_STOP to effectively exit from the CPU execution loop. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg : modified the commit log to comment the use of EXCP_HLT instead of POWERPC_EXCP_STOP] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190215161648.9600-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-22Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-feb-21-2019-v2' into staging MIPS queue for February 21st, 2019, v2 # gpg: Signature made Thu 21 Feb 2019 18:37:04 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-feb-21-2019-v2: target/mips: fulong2e: Dynamically generate SPD EEPROM data target/mips: fulong2e: Fix bios flash size hw/pci-host/bonito.c: Add PCI mem region mapped at the correct address target/mips: implement QMP query-cpu-definitions command tests/tcg: target/mips: Add wrappers for MSA integer compare instructions tests/tcg: target/mips: Change directory name 'bit-counting' to 'bit-count' tests/tcg: target/mips: Correct path to headers in some test source files hw/misc: mips_itu: Fix 32/64 bit issue in a line involving shift operator Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/mips: implement QMP query-cpu-definitions commandPavel Dovgalyuk
This patch enables QMP-based querying of the available CPU types for MIPS and MIPS64 platforms. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2019-02-21target/arm: Implement ARMv8.3-JSConvRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed a couple of comment typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Rearrange Floating-point data-processing (2 regs)Richard Henderson
There are lots of special cases within these insns. Split the major argument decode/loading/saving into no_output (compares), rd_is_dp, and rm_is_dp. We still need to special case argument load for compare (rd as input, rm as zero) and vcvt fixed (rd as input+output), but lots of special cases do disappear. Now that we have a full switch at the beginning, hoist the ISA checks from the code generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Split out vfp_helper.cRichard Henderson
Move all of the fp helpers out of helper.c into a new file. This is code movement only. Since helper.c has no copyright header, take the one from cpu.h for the new file. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Restructure disas_fp_int_convRichard Henderson
For opcodes 0-5, move some if conditions into the structure of a switch statement. For opcodes 6 & 7, decode everything at once with a second switch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Stop unintentional sign extension in pmu_initAaron Lindsay OS
This was introduced by commit bf8d09694ccc07487cd73d7562081fdaec3370c8 target/arm: Don't clear supported PMU events when initializing PMCEID1 and identified by Coverity (CID 1398645). Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190219144621.450-1-aaron@os.amperecomputing.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: v8M MPU should use background region as default, not alwaysPeter Maydell
The "background region" for a v8M MPU is a default which will be used (if enabled, and if the access is privileged) if the access does not match any specific MPU region. We were incorrectly using it always (by putting the condition at the wrong nesting level). This meant that we would always return the default background permissions rather than the correct permissions for a specific region, and also that we would not return the right information in response to a TT instruction. Move the check for the background region to the same place in the logic as the equivalent v8M MPUCheck() pseudocode puts it. This in turn means we must adjust the condition we use to detect matches in multiple regions to avoid false-positives. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190214113408.10214-1-peter.maydell@linaro.org
2019-02-18target/xtensa: implement wide branches and loopsMax Filippov
FLIX adds branch and loop instruction variants with 15- and 18-bit wide target offset. Implement them as additional names for the ordinary branch/loop opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: allow multiple names for single opcodeMax Filippov
There are opcodes that differ only in encoding or possible range of immediate arguments. Allow multiple names for single opcode translation table entry to reduce code duplication in that case. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: don't require opcode table sortingMax Filippov
Requirement for alphabetical opcode sorting in opcode tables is awkward and does not allow sharing implementation between multiple opcodes. Use hash tables to find opcodes by name. Move implementation from the translate.c to the helper.c to its only user and remove declaration from the cpu.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov
Don't run xtensa_finalize_config at the time of core registration, instead run it at the CPU class initialization. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: fixup test_mmuhifi_c3 overlayMax Filippov
xtensa-modules part of the test_mmuhifi_c3 core is missing fixes that returns XTENSA_UNDEFINED for undefined opcodes and marks all data structures static. Run sed script from target/xtensa/import_core.sh on it. This fixes test_sr tests for missing special registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190219' ↵Peter Maydell
into staging ppc patch queue 2019-02-19 Here's the next batch of ppc and spapr patches. Higlights are: * A bunch of improvements to TCG handling of vector instructions from Richard Henderson and Marc Cave-Ayland * Cleanup to the XICS interrupt controller from Greg Kurz, removing the special KVM subclasses which were a bad idea * Some refinements to the XIVE interrupt controller from Cédric Le Goater * Fix from Fabiano Rosas for a really dumb buffer overflow in the device tree code for memory hotplug * Code for allowing access to SPRs from the gdb stub from Fabiano Rosas * Assorted minor fixes and cleanups # gpg: Signature made Mon 18 Feb 2019 13:47:54 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.0-20190219: (43 commits) target/ppc: convert vmin* and vmax* to vector operations target/ppc: convert vadd*s and vsub*s to vector operations target/ppc: Split out VSCR_SAT to a vector field target/ppc: Add set_vscr_sat target/ppc: Use mtvscr/mfvscr for vmstate target/ppc: Add helper_mfvscr target/ppc: Remove vscr_nj and vscr_sat target/ppc: Use helper_mtvscr for reset and gdb target/ppc: Pass integer to helper_mtvscr target/ppc: convert xxsel to vector operations target/ppc: convert xxspltw to vector operations target/ppc: convert xxspltib to vector operations target/ppc: convert VSX logical operations to vector operations target/ppc: convert vsplt[bhw] to use vector operations target/ppc: convert vspltis[bhw] to use vector operations target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector operations target/ppc: convert VMX logical instructions to use vector operations xics: Drop the KVM ICS class spapr/irq: Use the "simple" ICS class for KVM xics: Handle KVM interrupt presentation from "simple" ICS code ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-18Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-02-18' into ↵Peter Maydell
staging QAPI patches for 2019-02-18 # gpg: Signature made Mon 18 Feb 2019 13:44:30 GMT # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2019-02-18: qapi: move RTC_CHANGE to the target schema qmp: Deprecate query-events in favor of query-qmp-schema Revert "qapi-events: add 'if' condition to implicit event enum" qapi: remove qmp_unregister_command() qapi: make query-cpu-definitions depend on specific targets qapi: make query-cpu-model-expansion depend on s390 or x86 qapi: make query-gic-capabilities depend on TARGET_ARM target.json: add a note about query-cpu* not being s390x-specific qapi: make s390 commands depend on TARGET_S390X qapi: make rtc-reset-reinjection and SEV depend on TARGET_I386 qapi: New module target.json build: Deal with all of QAPI's .o in qapi/Makefile.objs build-sys: move qmp-introspect per target qapi: Generate QAPIEvent stuff into separate files qapi: Prepare for system modules other than 'builtin' qapi: Clean up modular built-in code generation a bit qapi: Fix up documentation for recent commit a95291007b2 qapi: Belatedly document modular code generation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-18qapi: make query-cpu-definitions depend on specific targetsMarc-André Lureau
It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-15-armbru@redhat.com>
2019-02-18qapi: make query-cpu-model-expansion depend on s390 or x86Marc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-14-armbru@redhat.com>
2019-02-18qapi: make query-gic-capabilities depend on TARGET_ARMMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-13-armbru@redhat.com>
2019-02-18qapi: make s390 commands depend on TARGET_S390XMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-11-armbru@redhat.com>
2019-02-18qapi: make rtc-reset-reinjection and SEV depend on TARGET_I386Marc-André Lureau
Move rtc-reset-reinjection and SEV in target.json and make them conditional on TARGET_I386. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-10-armbru@redhat.com>
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