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2019-02-05target/arm: Default handling of BTYPE during translationRichard Henderson
The branch target exception for guarded pages has high priority, and only 8 instructions are valid for that case. Perform this check before doing any other decode. Clear BTYPE after all insns that neither set BTYPE nor exit via exception (DISAS_NORETURN). Not yet handled are insns that exit via DISAS_NORETURN for some other reason, like direct branches. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05target/arm: Cache the GP bit for a page in MemTxAttrsRichard Henderson
Caching the bit means that we will not have to re-walk the page tables to look up the bit during translation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190128223118.5255-6-richard.henderson@linaro.org [PMM: no need to OR in guarded bit status] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05target/arm: Add BT and BTYPE to tb->flagsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05target/arm: Add PSTATE.BTYPERichard Henderson
Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05target/arm: Introduce isar_feature_aa64_btiRichard Henderson
Also create field definitions for id_aa64pfr1 from ARMv8.5. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190128223118.5255-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
pci, pc, virtio: fixes, cleanups, features vhost user blk discard/write zeroes features misc cleanups and fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 05 Feb 2019 16:00:20 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: contrib/libvhost-user: cleanup casts r2d: fix build on mingw mmap-alloc: fix hugetlbfs misaligned length in ppc64 mmap-alloc: unfold qemu_ram_mmap() i386, acpi: cleanup build_facs by removing second unused argument fw_cfg: fix the life cycle and the name of "qemu_extra_params_fw" acpi: Make TPM 2.0 with TIS available as MSFT0101 hw/virtio: Use CONFIG_VIRTIO_PCI switch instead of CONFIG_PCI vhost-user-blk: add discard/write zeroes features support contrib/vhost-user-blk: fix the compilation issue pci/msi: export msi_is_masked() intel_iommu: reset intr_enabled when system reset intel_iommu: fix operator in vtd_switch_address_space hw: virtio-pci: drop DO_UPCAST include: update Linux headers to 4.21-rc1/5.0-rc1 scripts/update-linux-headers.sh: adjust for Linux 4.21-rc1 (or 5.0-rc1) contrib/libvhost-user: switch to uint64_t virtio: add checks for the size of the indirect table Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05contrib/vhost-user-blk: fix the compilation issuePeter Xu
Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-02-05i386: hvf: Fix smp boot hangsHeiher
The machine that with hvf accelerator and smp sometimes boot hangs because all processors are executing instructions at startup, including early I/O emulations. We should just allow the bootstrap processor to initialize the machine and then to wake up slave processors by interrupt. Signed-off-by: Heiher <r@hev.cc> Message-Id: <20190123073402.28465-1-r@hev.cc> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05gdbstub: Fix i386/x86_64 machine description and add control registersDoug Gale
The machine description we send is being (silently) thrown on the floor by GDB and GDB silently uses the default machine description, because the xml parse fails on <feature> nested within <feature>. Changes to the xml in qemu source code have no effect. In addition, the default machine description has fs_base, which fails to be retrieved, which breaks the whole register window. Add it and the other control registers. Signed-off-by: Doug Gale <doug16k@gmail.com> Message-Id: <20190124040457.2546-1-doug16k@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05i386: hvf: Don't miss 16-bit displacementRoman Bolshakov
In 16-bit addressing mode, when Mod = 0 and R/M = 6, decoded displacement doesn't reach decode_linear_addr and gets lost. Instructions that involve the combination of ModRM always get a pointer with zero offset from the beginning of DS segment. The change fixes drawing in F-BIRD from day 1 of '18 advent calendar. Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20190125154743.14498-1-r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05target-i386: hvf: remove MPX supportPaolo Bonzini
MPX support is being phased out by Intel and actually I am not sure that OS X has ever enabled it in XCR0. Drop it from the Hypervisor.framework acceleration. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05Revert "i386: Add CPUID bit for PCONFIG"Robert Hoo
This reverts commit 5131dc433df54b37e8e918d8fba7fe10344e7a7b. For new instruction 'PCONFIG' will not be exposed to guest. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1545227081-213696-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05i386: remove the 'INTEL_PT' CPUID bit from named CPU modelsPaolo Bonzini
Processor tracing is not yet implemented for KVM and it will be an opt in feature requiring a special module parameter. Disable it, because it is wrong to enable it by default and it is impossible that no one has ever used it. Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05i386: remove the new CPUID 'PCONFIG' from Icelake-Server CPU modelRobert Hoo
PCONFIG is not available to guests; it must be specifically enabled using the PCONFIG_ENABLE execution control. Disable it, because no one can ever use it. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1545227081-213696-2-git-send-email-robert.hu@linux.intel.com> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05Merge remote-tracking branch 'remotes/xtensa/tags/20190204-xtensa' into stagingPeter Maydell
target/xtensa: SMP updates and various fixes - fix CPU wakeup on runstall changes; expose runstall as an IRQ line; - place mini-bootloader at the BSP reset vector; - expose CPU core frequency in XTFPGA board FPGA register; - rearrange access to external interrupts of xtensa cores; - add MX interrupt distributor and use it on SMP XTFPGA boards; - add test_mmuhifi_c3 xtensa core variant; - raise number of CPUs that can be instantiated on XTFPGA boards. # gpg: Signature made Mon 04 Feb 2019 18:59:32 GMT # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190204-xtensa: hw/xtensa: xtfpga: raise CPU number limit target/xtensa: add test_mmuhifi_c3 core hw/xtensa: xtfpga: use MX PIC for SMP target/xtensa: add MX interrupt controller target/xtensa: expose core runstall as an IRQ line target/xtensa: rearrange access to external interrupts target/xtensa: drop function xtensa_timer_irq target/xtensa: fix access to the INTERRUPT SR hw/xtensa: xtfpga: use core frequency hw/xtensa: xtfpga: fix bootloader placement in SMP target/xtensa: add qemu_cpu_kick to xtensa_runstall Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-04s390x/tcg: Don't model FP registers as globalsDavid Hildenbrand
As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04s390x: remove direct reference to mem_path global from s390x codeIgor Mammedov
I plan to deprecate -mem-path option and replace it with memory-backend, for that it's necessary to get rid of mem_path global variable. Do it for s390x case, replacing it with alternative way to enable 1Mb hugepages capability. Todo that replace qemu_mempath_getpagesize() with qemu_getrampagesize() which also checks for -mem-path provided RAM. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <1548834906-133241-1-git-send-email-imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04target/s390x: define TCG_GUEST_DEFAULT_MO for MTTCGAlex Bennée
MTTCG should be enabled by default whenever the memory model allows it. s390x was missing its definition of TCG_GUEST_DEFAULT_MO meaning the user had to manually specify --accel tcg,thread=multi. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: David Hildenbrand <david@redhat.com> Message-Id: <20190118171848.27332-1-alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in int_helper.cMark Cave-Ayland
Following on from the previous work, there are numerous endian-related hacks in int_helper.c that can now be replaced with Vsr* macros. There are also a few places where the VECTOR_FOR_INORDER_I macro can be replaced with a normal iterator since the processing order is irrelevant. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: remove ROTRu32 and ROTRu64 macros from int_helper.cMark Cave-Ayland
Richard points out that these macros suffer from a -fsanitize=shift bug in that they improperly handle n == 0 turning it into a shift by 32/64 respectively. Replace them with QEMU's existing ror32() and ror64() functions instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: simplify VEXT_SIGNED macro in int_helper.cMark Cave-Ayland
As pointed out by Richard: it does not need the mask argument, nor does it need the recast argument. The masking is implied by the cast argument, and the recast is implied by the assignment. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: eliminate use of EL_IDX macros from int_helper.cMark Cave-Ayland
These macros can be eliminated by instead using the relavant Vsr* macros in the few locations where they appear. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: eliminate use of HI_IDX and LO_IDX macros from int_helper.cMark Cave-Ayland
The original purpose of these macros was to correctly reference the high and low parts of the VSRs regardless of the host endianness. Replace these direct references to high and low parts with the relevant VsrD macro instead, and completely remove the now-unused HI_IDX and LO_IDX macros. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: rework vmul{e,o}{s,u}{b,h,w} instructions to use Vsr* macrosMark Cave-Ayland
The current implementations make use of the endian-specific macros HI_IDX and LO_IDX directly to calculate array offsets. Rework the implementation to use the Vsr* macros so that these per-endian references can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: rework vmrg{l,h}{b,h,w} instructions to use Vsr* macrosMark Cave-Ayland
The current implementations make use of the endian-specific macros MRGLO/MRGHI and also reference HI_IDX and LO_IDX directly to calculate array offsets. Rework the implementation to use the Vsr* macros so that these per-endian references can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04ppc: remove the interrupt presenters from under PowerPCCPUCédric Le Goater
These fields have now been replaced by equivalents under the machine data. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc: implement complete set of Vsr* macrosMark Cave-Ayland
This prepares us for eliminating the use of direct array access within the VMX instruction implementations. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-04target/ppc/kvm: Drop useless include directiveGreg Kurz
It has been there since the enablement of PR KVM for PAPR, ie, commit f61b4bedaf35 in 2011. Not sure why at that time, but it is definitely not needed with the current code. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-01target/arm: fix decoding of B{,L}RA{A,B}Remi Denis-Courmont
A flawed test lead to the instructions always being treated as unallocated encodings. Fixes: https://bugs.launchpad.net/bugs/1813460 Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01target/arm: fix AArch64 virtual address space sizeRemi Denis-Courmont
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address, extension (yet), the VA address space is 48-bits plus a sign bit. User mode can only handle the positive half of the address space, so that makes a limit of 48 bits. (With LVA, it would be 53 and 52 bits respectively.) The incorrectly large address space conflicts with PAuth instructions, which use bits 48-54 and 56-63 for the pointer authentication code. This also conflicts with (as yet unsupported by QEMU) data tagging and with the ARMv8.5-MTE extension. Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01target/arm: Always enable pac keys for user-onlyRichard Henderson
Drop the pac properties. This approach cannot work as written because the properties are applied before arm_cpu_reset, which zeros SCTLR_EL1 (amongst everything else). We can re-introduce the properties if they turn out to be useful. But since linux 5.0 enables all of the keys, they may not be. Fixes: 1ae9cfbd470 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01arm: Clarify the logic of set_pc()Julia Suvorova
Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for “Configure the PC, as was done in the ELF file” and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Signed-off-by: Julia Suvorova <jusual@mail.ru> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190129121817.7109-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01target/arm: Enable API, APK bits in SCR, HCRRichard Henderson
These bits become writable with the ARMv8.3-PAuth extension. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190129143511.12311-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01target/arm: Add a timer to predict PMU counter overflowAaron Lindsay OS
Make PMU overflow interrupts more accurate by using a timer to predict when they will overflow rather than waiting for an event to occur which allows us to otherwise check them. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190124162401.5111-3-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01target/arm: Send interrupts on PMU counter overflowAaron Lindsay OS
Whenever we notice that a counter overflow has occurred, send an interrupt. This is made more reliable with the addition of a timer in a follow-on commit. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190124162401.5111-2-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01target/arm/translate-a64: Fix mishandling of size in FCMLA decodePeter Maydell
In disas_simd_indexed(), for the case of "complex fp", each indexable element is a complex pair, so the total size is twice that indicated in the 'size' field in the encoding. We were trying to do this "double the size" operation with a left shift by 1, but this is incorrect because the 'size' field is a MO_8/MO_16/MO_32/MO_64 value, and doubling the size should be done by a simple increment. This meant we were mishandling FCMLA (by element) of values where the real and imaginary parts are 32-bit floats, and would incorrectly UNDEF this encoding. (No other insns take this code path, and for 16-bit floats it happens that 1 << 1 and 1 + 1 are both the same). Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190129140411.682-3-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Fix FCMLA decoding errorPeter Maydell
The FCMLA (by element) instruction exists in the "vector x indexed element" encoding group, but not in the "scalar x indexed element" group. Correctly UNDEF the unallocated encodings. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190129140411.682-2-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode SDOT and UDOTPeter Maydell
In the AdvSIMD scalar x indexed element and vector x indexed element encoding group, the SDOT and UDOT instructions are vector only, and their opcode is unallocated in the scalar group. Correctly UNDEF this unallocated encoding. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-8-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode FP insnsPeter Maydell
In the encoding groups * floating-point data-processing (1 source) * floating-point data-processing (2 source) * floating-point data-processing (3 source) * floating-point immediate * floating-point compare * floating-ponit conditional compare * floating-point conditional select bit 31 is M and bit 29 is S (and bit 30 is 0, already checked at this point in the decode). None of these groups allocate any encoding for M=1 or S=1. We checked this in disas_fp_compare(), disas_fp_ccomp() and disas_fp_csel(), but missed it in disas_fp_1src(), disas_fp_2src(), disas_fp_3src() and disas_fp_imm(). We also missed that in the fp immediate encoding the imm5 field must be all zeroes. Correctly UNDEF the unallocated encodings here. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-7-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode add/sub extended registerPeter Maydell
In the "add/subtract (extended register)" encoding group, the "opt" field in bits [23:22] must be zero. Correctly UNDEF the unallocated encodings where this field is not zero. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode SIMD ld/st singlePeter Maydell
In the AdvSIMD load/store single structure encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Bit 31 must also be zero (a check we got right in ldst_multiple but not here). Correctly UNDEF these unallocated encodings. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode SIMD ld/st multiplePeter Maydell
In the AdvSIMD load/store multiple structures encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Correctly UNDEF the currently unallocated encodings which have non-zeroes in those bits. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-4-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode PRFMPeter Maydell
The PRFM prefetch insn in the load/store with imm9 encodings requires idx field 0b00; we were underdecoding this by only checking !is_unpriv (which is equivalent to idx != 2). Correctly UNDEF the unallocated encodings where idx == 0b01 and 0b11 as well as 0b10. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-3-peter.maydell@linaro.org
2019-02-01target/arm/translate-a64: Don't underdecode system instructionsPeter Maydell
The "system instructions" and "system register move" subcategories of "branches, exception generating and system instructions" for A64 only apply if bits [23:22] are zero; other values are currently unallocated. Correctly UNDEF these unallocated encodings. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20190125182626.9221-2-peter.maydell@linaro.org
2019-01-31Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-pull-request' into staging - add device category (edu, i8042, sd memory card) - code clean-up - LGPL information clean-up - fix typo (acpi) # gpg: Signature made Wed 30 Jan 2019 13:21:50 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: virtio-blk: remove duplicate definition of VirtIOBlock *s pointer hw/block: clean up stale xen_disk trace entries target/m68k: Fix LGPL information in the file headers target/s390x: Fix LGPL version in the file header comments tcg: Fix LGPL version number target/tricore: Fix LGPL version number target/openrisc: Fix LGPL version number COPYING.LIB: Synchronize the LGPL 2.1 with the version from gnu.org Don't talk about the LGPL if the file is licensed under the GPL hw: sd: set category of the sd memory card hw: input: set category of the i8042 device typo: apci->acpi hw: edu: set category of the edu device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-30target/m68k: Fix LGPL information in the file headersThomas Huth
It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Also some files mention the GPL instead of the LGPL after declaring that the files are licensed under the LGPL, so change these spots to use LGPL, too. Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1548769438-28942-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30target/s390x: Fix LGPL version in the file header commentsThomas Huth
It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <1548769067-20792-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30target/tricore: Fix LGPL version numberThomas Huth
It's either "GNU *Library* General Public version 2" or "GNU Lesser General Public version *2.1*", but there was no "version 2.0" of the "Lesser" library. So assume that version 2.1 is meant here. Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1548252536-6242-4-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth
It's either "GNU *Library* General Public version 2" or "GNU Lesser General Public version *2.1*", but there was no "version 2.0" of the "Lesser" library. So assume that version 2.1 is meant here. Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1548252536-6242-3-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30Don't talk about the LGPL if the file is licensed under the GPLThomas Huth
Some files claim that the code is licensed under the GPL, but then suddenly suggest that the user should have a look at the LGPL. That's of course non-sense, replace it with the correct GPL wording instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1548255083-8190-1-git-send-email-thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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