aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)Author
2018-10-18target/arm: Convert to HAVE_CMPXCHG128Richard Henderson
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-18target/i386: Convert to HAVE_CMPXCHG128Richard Henderson
Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-18target/unicore32: remove tlb_flush from uc32_init_fnEmilio G. Cota
As far as I can tell tlb_flush does not need to be called this early. tlb_flush is eventually called after the CPU has been realized. This change paves the way to the introduction of tlb_init, which will be called from cpu_exec_realizefn. Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20181009174557.16125-3-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-18target/alpha: remove tlb_flush from alpha_cpu_initfnEmilio G. Cota
As far as I can tell tlb_flush does not need to be called this early. tlb_flush is eventually called after the CPU has been realized. This change paves the way to the introduction of tlb_init, which will be called from cpu_exec_realizefn. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20181009174557.16125-2-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-18target/mips: Add opcodes for nanoMIPS EVA instructionsDimitrije Nikolic
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PHStefan Markovic
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by Coverity (CID 1395627). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>Matthew Fortune
Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions. Their handling was permuted. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Matthew Fortune <matthew.fortune@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Implement hardware page table walker for MIPS32Yongbok Kim
Implement hardware page table walker. This implementation is limiter only to MIPS32. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add reset state for PWSize and PWField registersYongbok Kim
Add reset state for PWSize and PWField registers. The reset state is different for pre-R6 and R6 (and post-R6) ISAa. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add CP0 PWCtl registerYongbok Kim
Add PWCtl register (CP0 Register 5, Select 6). The PWCtl register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: PWEn (31) - Hardware Page Table walker enable PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only) XK (28) - If 1, walker handles xkseg (MIPS64 only) XS (27) - If 1, walker handles xsseg (MIPS64 only) XU (26) - If 1, walker handles xuseg (MIPS64 only) DPH (7) - Dual Page format of Huge Page support HugePg (6) - Huge Page PTE supported in Directory levels PSn (5..0) - Bit position of PTEvld in Huge Page PTE Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add CP0 PWSize registerYongbok Kim
Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: BDW (37..32) Base Directory index width (MIPS64 only) GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add CP0 PWField registerYongbok Kim
Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: MIPS64: BDI (37..32) - Base Directory index GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift MIPS32: GDW (29..24) - Global Directory index UDW (23..18) - Upper Directory index MDW (17..12) - Middle Directory index PTW (11..6 ) - Page Table index PTEW ( 5..0 ) - Page Table Entry shift Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add CP0 PWBase registerYongbok Kim
Add PWBase register (CP0 Register 5, Select 5). The PWBase register contains the Page Table Base virtual address. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add CP0 Config2 to DisasContextStefan Markovic
Add field corresponding to CP0 Config2 to DisasContext. This is needed for availability control via Config2 bits. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Improve DSP R2/R3-related namingStefan Markovic
Do following replacements: ASE_DSPR2 -> ASE_DSP_R2 ASE_DSPR3 -> ASE_DSP_R3 MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2 MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3 check_dspr2() -> check_dsp_r2() check_dspr3() -> check_dsp_r3() and several other similar minor replacements. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add availability control for DSP R3 ASEStefan Markovic
Add infrastructure for availability control for DSP R3 ASE MIPS instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but this is likely to be changed in near future. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add bit definitions for DSP R3 ASEStefan Markovic
Add DSP R3 ASE related bit definition for insn_flags and hflags. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)Philippe Mathieu-Daudé
Distribute bits 56-63 vendor-specific ASEs as follows: - bits 0-31 MIPS base instruction sets - bits 32-47 MIPS ASEs - bits 48-55 vendor-specific base instruction sets - bits 56-63 vendor-specific ASEs Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Increase 'supported ISAs/ASEs' flag holder sizePhilippe Mathieu-Daudé
Increase the size of insn_flags holder size to 64 bits. This is needed for future extensions since existing bits are almost all used. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add opcode values of MXU ASEAleksandar Markovic
Add opcode values for all instructions in MXU ASE. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add organizational chart of MXU ASEAleksandar Markovic
Add a comment that contains an organizational chart of MXU ASE instructions. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add assembler mnemonics list for MXU ASEAleksandar Markovic
Add a comment that contains a list all MXU instructions, expressed in assembler mnemonics. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add basic description of MXU ASEAleksandar Markovic
Add a comment that contains a basic description of MXU ASE. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add a comment before each CP0 register section in cpu.hAleksandar Markovic
Add a comment before each CP0 register section in CPUMIPSState definition, thus visually separating these sections. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18target/mips: Add a comment with an overview of CP0 registersAleksandar Markovic
Add a comment with an overview of CP0 registers close to the definition of their corresponding fields in CPUMIPSState. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18Merge remote-tracking branch ↵Peter Maydell
'remotes/huth-gitlab/tags/pull-request-2018-10-17' into staging - Updates for qtest entries in test/Makefile.include - Simple updates for some shell scripts - Misc simple patches for files without regular subsystem pull requests # gpg: Signature made Wed 17 Oct 2018 08:20:35 BST # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" # gpg: aka "Thomas Huth <thuth@redhat.com>" # gpg: aka "Thomas Huth <huth@tuxfamily.org>" # gpg: aka "Thomas Huth <th.huth@posteo.de>" # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2018-10-17: configure: remove glib_subprocess check hw/core/generic-loader: Compile only once, not for each target cpu: Provide a proper prototype for target_words_bigendian() in a header hw/core/generic-loader: Set a category for the generic-loader device qemu/compiler: Wrap __attribute__((flatten)) in a macro mailmap: Fix Reimar Döffinger name show-fixed-bugs.sh: Modern shell scripting (use $() instead of ``) git-submodule.sh: Modern shell scripting (use $() instead of ``) archive-source.sh: Modern shell scripting (use $() instead of ``) MAINTAINERS: update block/sheepdog maintainers gdbstub: Remove unused include tests: remove gcov-files- variables tests: Prevent more accidental test disabling target/cris/translate: Get rid of qemu_log_separate() qemu-common.h: update copyright date to 2018 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
* Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark
This patch makes op_helper.c contain only instruction operation helpers used by translate.c and moves any unrelated cpu helpers into cpu_helper.c. No logic is changed by this patch. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
Change the API of riscv_set_local_interrupt to take a write mask and value to allow setting and clearing of multiple local interrupts atomically in a single call. Rename the new function to riscv_cpu_update_mip. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-16target/hppa: Raise exception 26 on emulated hardwareHelge Deller
On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults, while all later chips (>= PA7100) generate either trap #26, #27 or #28 (depending on the fault type). Since the current qemu emulation emulates a B160L machine (with a PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero. With the patch we now get the correct output (I tested against real hardware): Kernel Fault: Code=26 (Data memory access rights trap) instead of: Kernel Fault: Code=18 (Data memory protection/unaligned access trap) Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20181007205153.GA30270@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-16target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/writePeter Maydell
The get_phys_addr() functions take a pointer to an ARMMMUFaultInfo struct, which they fill in only if a fault occurs. This means that the caller must always zero-initialize the struct before passing it in. We forgot to do this in v7m_stack_read() and v7m_stack_write(). Correct the error. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181011172057.9466-1-peter.maydell@linaro.org
2018-10-16target/arm: Mask PMOVSR writes based on supported countersAaron Lindsay
This is an amendment to my earlier patch: commit 7ece99b17e832065236c07a158dfac62619ef99b Author: Aaron Lindsay <alindsay@codeaurora.org> Date: Thu Apr 26 11:04:39 2018 +0100 target/arm: Mask PMU register writes based on PMCR_EL0.N Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181010203735.27918-3-aclindsa@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IOAaron Lindsay
I previously fixed this for PMINTENSET_EL1, but missed these. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181010203735.27918-2-aclindsa@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target/arm: Add the Cortex-A72Edgar E. Iglesias
Add the ARM Cortex-A72. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181011021931.4249-11-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target-arm: powerctl: Enable HVC when starting CPUs to EL2Edgar E. Iglesias
When QEMU provides the equivalent of the EL3 firmware, we need to enable HVCs in scr_el3 when turning on CPUs that target EL2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target/cris/translate: Get rid of qemu_log_separate()Thomas Huth
The gen_BUG() function calls already cpu_abort(), which prints the information to stderr and the log already. So instead of additionally printing the dc->pc via fprintf() and qemu_log here, too, we can simply pass this information to cpu_abort() instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-16target/arm: Fix cortex-a7 id_isar0Richard Henderson
The incorrect value advertised only thumb2 div without arm div. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181008212205.17752-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target/arm: Align cortex-r5 id_isar0Richard Henderson
The missing nibble made it more difficult to read. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181008212205.17752-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target/arm: Define fields of ISAR registersRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181008212205.17752-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16target/arm: Fix aarch64_sve_change_el wrt EL0Richard Henderson
At present we assert: arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed. The comment in arm_el_is_aa64 explains why asking about EL0 without extra information is impossible. Add an extra argument to provide it from the surrounding context. Fixes: 0ab5953b00b3 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181008212205.17752-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-12s390x/kvm: enable AP instruction interpretation for guestTony Krowiak
Let's use the KVM_SET_DEVICE_ATTR ioctl to enable hardware interpretation of AP instructions executed on the guest. If the S390_FEAT_AP feature is switched on for the guest, AP instructions must be interpreted by default; otherwise, they will be intercepted. This attribute setting may be overridden by a device. For example, a device may want to provide AP instructions to the guest (i.e., S390_FEAT_AP turned on), but it may want to emulate them. In this case, the AP instructions executed on the guest must be intercepted; so when the device is realized, it must disable interpretation. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20181010170309.12045-4-akrowiak@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-12s390x/cpumodel: Set up CPU model for AP device supportTony Krowiak
A new CPU model feature and two new CPU model facilities are introduced to support AP devices for a KVM guest. CPU model features: 1. The S390_FEAT_AP CPU model feature indicates whether AP instructions are available to the guest. This feature will be enabled only if the AP instructions are available on the linux host as determined by the availability of the KVM_S390_VM_CRYPTO_ENABLE_APIE VM attribute which is exposed by KVM only if the AP instructions are available on the host. This feature must be turned on from userspace to execute AP instructions on the KVM guest. The QEMU command line to turn this feature on looks something like this: qemu-system-s390x ... -cpu xxx,ap=on ... This feature will be supported for zEC12 and newer CPU models. The feature will not be supported for older models because there are few older systems on which to test and the older crypto cards will be going out of service in the relatively near future. CPU model facilities: 1. The S390_FEAT_AP_QUERY_CONFIG_INFO feature indicates whether the AP Query Configuration Information (QCI) facility is available to the guest as determined by whether the facility is available on the host. This feature will be exposed by KVM only if the QCI facility is installed on the host. 2. The S390_FEAT_AP_FACILITY_TEST feature indicates whether the AP Facility Test (APFT) facility is available to the guest as determined by whether the facility is available on the host. This feature will be exposed by KVM only if APFT is installed on the host. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20181010170309.12045-3-akrowiak@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-12target/s390x/excp_helper: Remove DPRINTF() macroThomas Huth
Debug macros that are disabled by default should be avoided (since the code bit-rots quite easily). Thus turn these debug prints into proper qemu_log_mask(CPU_LOG_xxx, ...) statements instead. The DPRINTF statements in do_[ext|io|mchk]_interrupt can even be removed completely since we can log the information in a central place, s390_cpu_do_interrupt, instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1538751601-7433-1-git-send-email-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-09s390x/tcg: always enable AFP for linux-userDavid Hildenbrand
linux-user should always enable AFP, otherwise our emulated binary might crash once it tries to make use of additional floating-point registers or instructions. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alex Bennée <alex.bennee@linaro.org> Fixes: db0504154e ("s390x/tcg: check for AFP-register, BFP and DFP data exceptions") Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Add v8M stack checks for MSR to SP_NSPeter Maydell
Updating the NS stack pointer via MSR to SP_NS should include a check whether the new SP value is below the stack limit. No other kinds of update to the various stack pointer and limit registers via MSR should perform a check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-14-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for VLDM/VSTMPeter Maydell
Add the v8M stack checks for the VLDM/VSTM (aka VPUSH/VPOP) instructions. This code is currently unreachable because we haven't yet implemented M profile floating point support, but since the change is simple, we add it now because otherwise we're likely to forget to do it later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-13-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for Thumb push/popPeter Maydell
Add v8M stack checks for the 16-bit Thumb push/pop encodings: STMDB, STMFD, LDM, LDMIA, LDMFD. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-12-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for T32 load/store singlePeter Maydell
Add v8M stack checks for the instructions in the T32 "load/store single" encoding class: these are the "immediate pre-indexed" and "immediate, post-indexed" LDR and STR instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-11-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for Thumb2 LDM/STMPeter Maydell
Add the v8M stack checks for: * LDM (T2 encoding) * STM (T2 encoding) This includes the 32-bit encodings of the instructions listed in v8M ARM ARM rule R_YVWT as * LDM, LDMIA, LDMFD * LDMDB, LDMEA * POP (multiple registers) * PUSH (muliple registers) * STM, STMIA, STMEA * STMDB, STMFD We perform the stack limit before doing any other part of the load or store. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-10-peter.maydell@linaro.org
2018-10-08target/arm: Add v8M stack checks for LDRD/STRD (imm)Peter Maydell
Add the v8M stack checks for: * LDRD (immediate) * STRD (immediate) Loads and stores are more complicated than ADD/SUB/MOV, because we must ensure that memory accesses below the stack limit are not performed, so we can't simply do the check when we actually update SP. For these instructions, if the stack limit check triggers we must not: * perform any memory access below the SP limit * update PC, SP or the load/store base register but it is IMPDEF whether we: * perform any accesses above or equal to the SP limit * update destination registers for loads For QEMU we choose to always check the limit before doing any other part of the load or store, so we won't update any registers or perform any memory accesses. It is UNKNOWN whether the limit check triggers for a load or store where the initial SP value is below the limit and one of the stores would be below the limit, but the writeback moves SP to above the limit. For QEMU we choose to trigger the check in this situation. Note that limit checks happen only for loads and stores which update SP via writeback; they do not happen for loads and stores which simply use SP as a base register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-9-peter.maydell@linaro.org
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 20:30:56 +0000