slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-02-27	target/riscv: Add the force HS exception mode	Alistair Francis
2020-02-27	target/riscv: Add the virtulisation mode	Alistair Francis
2020-02-27	target/riscv: Rename the H irqs to VS irqs	Alistair Francis
2020-02-27	target/riscv: Add support for the new execption numbers	Alistair Francis
2020-02-27	target/riscv: Add the Hypervisor CSRs to CPUState	Alistair Francis
2020-02-27	target/riscv: Add the Hypervisor extension	Alistair Francis
2020-02-27	target/riscv: Convert MIP CSR to target_ulong	Alistair Francis
2020-02-27	Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200227' into staging	Peter Maydell
2020-02-27	s390x: Rename and use constants for short PSW address and mask	Janosch Frank
2020-02-26	s390/sclp: improve special wait psw logic	Christian Borntraeger
2020-02-26	s390x: Add missing vcpu reset functions	Janosch Frank
2020-02-26	target/s390x/translate: Fix RNSBG instruction	Thomas Huth
2020-02-25	target/riscv: progressively load the instruction during decode	Alex Bennée
2020-02-25	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	Paolo Bonzini
2020-02-25	target/i386: check for empty register in FXAM	Paolo Bonzini
2020-02-21	target/arm: Set MVFR0.FPSP for ARMv5 cpus	Richard Henderson
2020-02-21	target/arm: Use isar_feature_aa32_simd_r32 more places	Richard Henderson
2020-02-21	target/arm: Rename isar_feature_aa32_simd_r32	Richard Henderson
2020-02-21	target/arm: Convert PMULL.8 to gvec	Richard Henderson
2020-02-21	target/arm: Convert PMULL.64 to gvec	Richard Henderson
2020-02-21	target/arm: Convert PMUL.8 to gvec	Richard Henderson
2020-02-21	target/arm: Vectorize USHL and SSHL	Richard Henderson
2020-02-21	target/arm: Correctly implement ACTLR2, HACTLR2	Peter Maydell
2020-02-21	target/arm: Use FIELD_EX32 for testing 32-bit fields	Peter Maydell
2020-02-21	target/arm: Use isar_feature function for testing AA32HPD feature	Peter Maydell
2020-02-21	target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks	Peter Maydell
2020-02-21	target/arm: Correct handling of PMCR_EL0.LC bit	Peter Maydell
2020-02-21	target/arm: Correct definition of PMCRDP	Peter Maydell
2020-02-21	target/arm: Provide ARMv8.4-PMU in '-cpu max'	Peter Maydell
2020-02-21	target/arm: Implement ARMv8.4-PMU extension	Peter Maydell
2020-02-21	target/arm: Implement ARMv8.1-PMU extension	Peter Maydell
2020-02-21	target/arm: Read debug-related ID registers from KVM	Peter Maydell
2020-02-21	target/arm: Move DBGDIDR into ARMISARegisters	Peter Maydell
2020-02-21	target/arm: Stop assuming DBGDIDR always exists	Peter Maydell
2020-02-21	target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks	Peter Maydell
2020-02-21	target/arm: Define an aa32_pmu_8_1 isar feature test function	Peter Maydell
2020-02-21	target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field	Peter Maydell
2020-02-21	target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1	Peter Maydell
2020-02-21	target/arm: Factor out PMU register definitions	Peter Maydell
2020-02-21	target/arm: Define and use any_predinv isar_feature test	Peter Maydell
2020-02-21	target/arm: Add isar_feature_any_fp16 and document naming/usage conventions	Peter Maydell
2020-02-21	target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan	Peter Maydell
2020-02-21	target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers	Peter Maydell
2020-02-21	target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid	Richard Henderson
2020-02-21	target/arm: Remove ttbr1_valid check from get_phys_addr_lpae	Richard Henderson
2020-02-21	target/arm: Fix select for aa64_va_parameters_both	Richard Henderson
2020-02-21	target/arm: Use bit 55 explicitly for pauth	Richard Henderson
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD INS	Richard Henderson
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN	Richard Henderson
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX	Richard Henderson