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2020-03-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell
2020-02-28target/arm: Implement ARMv8.3-CCIDXPeter Maydell
2020-02-28target/arm: Implement v8.4-RCPCPeter Maydell
2020-02-28target/arm: Implement v8.3-RCPCPeter Maydell
2020-02-28target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0Peter Maydell
2020-02-28target/arm: Split VMINMAXNM decodeRichard Henderson
2020-02-28target/arm: Split VFM decodeRichard Henderson
2020-02-28target/arm: Add formats for some vfp 2 and 3-register insnsRichard Henderson
2020-02-28target/arm: Remove ARM_FEATURE_VFP*Richard Henderson
2020-02-28target/arm: Move the vfp decodetree calls next to the base isaRichard Henderson
2020-02-28target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson
2020-02-28target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insnRichard Henderson
2020-02-28target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson
2020-02-28target/arm: Add missing checks for fpsp_v2Richard Henderson
2020-02-28target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3Richard Henderson
2020-02-28target/arm: Perform fpdp_v2 check firstRichard Henderson
2020-02-28target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfpRichard Henderson
2020-02-28target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}Richard Henderson
2020-02-28target/arm: Rename isar_feature_aa32_fpdp_v2Richard Henderson
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson
2020-02-28target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfnRichard Henderson
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis
2020-02-27target/riscv: Implement second stage MMUAlistair Francis
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis
2020-02-27target/riscv: Remove the hret instructionAlistair Francis
2020-02-27target/riscv: Add hfence instructionsAlistair Francis
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis
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