aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)Author
2018-10-08target/arm: Define new TBFLAG for v8M stack checkingPeter Maydell
The Arm v8M architecture includes hardware stack limit checking. When certain instructions update the stack pointer, if the new value of SP is below the limit set in the associated limit register then an exception is taken. Add a TB flag that tracks whether the limit-checking code needs to be emitted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181002163556.10279-2-peter.maydell@linaro.org
2018-10-08target/arm: Pass TCGMemOpIdx to sve memory helpersRichard Henderson
There is quite a lot of code required to compute cpu_mem_index, or even put together the full TCGMemOpIdx. This can easily be done at translation time. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite vector gather first-fault loadsRichard Henderson
This implements the feature for softmmu, and moves the main loop out of a macro and into a function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite vector gather storesRichard Henderson
This fixes the endianness problem for softmmu, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite vector gather loadsRichard Henderson
This fixes the endianness problem for softmmu, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Split contiguous stores for endiannessRichard Henderson
We can choose the endianness at translation time, rather than re-computing it at execution time. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Split contiguous loads for endiannessRichard Henderson
We can choose the endianness at translation time, rather than re-computing it at execution time. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite helper_sve_st[1234]*_rRichard Henderson
This fixes the endianness problem for softmmu, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite helper_sve_ld[234]*_rRichard Henderson
Use the same *_tlb primitives as we use for ld1. For linux-user, this hoists the set of helper_retaddr. For softmmu, hoists the computation of the current mmu_idx outside the loop, fixes the endianness problem, and moves the main loop out of a macro and into an inlined function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Rewrite helper_sve_ld1*_r using pagesRichard Henderson
Uses tlb_vaddr_to_host for correct operation with softmmu. Optimize for accesses within a single page or pair of pages. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Clear unused predicate bits for LD1RQRichard Henderson
The 16-byte load only uses 16 predicate bits. But while reusing the other load infrastructure, we find other bits that are set and trigger an assert. To avoid this and retain the assert, zero-extend the predicate that we pass to the LD1 helper. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Adjust aarch64_cpu_dump_state for system mode SVERichard Henderson
Use the existing helpers to determine if (1) the fpu is enabled, (2) sve state is enabled, and (3) the current sve vector length. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Handle SVE vector length changes in system modeRichard Henderson
SVE vector length can change when changing EL, or when writing to one of the ZCR_ELn registers. For correctness, our implementation requires that predicate bits that are inaccessible are never set. Which means noticing length changes and zeroing the appropriate register bits. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Pass in current_el to fp and sve_exception_elRichard Henderson
We are going to want to determine whether sve is enabled for EL other than current. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Adjust sve_exception_elRichard Henderson
Check for EL3 before testing CPTR_EL3.EZ. Return 0 when the exception should be routed via AdvSIMDFPAccessTrap. Mirror the structure of CheckSVEEnabled more closely. Fixes: 5be5e8eda78 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Define ID_AA64ZFR0_EL1Richard Henderson
Given that the only field defined for this new register may only be 0, we don't actually need to change anything except the name. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08target/arm: Don't read r4 from v8M exception stackframe twicePeter Maydell
A cut-and-paste error meant we were reading r4 from the v8M callee-saves exception stack frame twice. This is harmless since it just meant we did two memory accesses to the same location, but it's unnecessary. Delete it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002150304.2287-1-peter.maydell@linaro.org
2018-10-08target/arm: Correct condition for v8M callee stack pushPeter Maydell
In v7m_exception_taken() we were incorrectly using a "LR bit EXCRET.ES is 1" check when it should be 0 (compare the pseudocode ExceptionTaken() function). This meant we didn't stack the callee-saved registers when tailchaining from a NonSecure to a Secure exception. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002145940.30931-1-peter.maydell@linaro.org
2018-10-08target/arm: fix code comments errorDongjiu Geng
The parameter of kvm_arm_init_cpreg_list() is ARMCPU instead of CPUState, so correct the note to make it match the code. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Message-id: 1538069046-5757-1-git-send-email-gengdongjiu@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-04s390x/tcg: refactor specification checkingDavid Hildenbrand
We can fit this nicely into less LOC, without harming readability. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: fix FP register pair checksDavid Hildenbrand
Valid register pairs are 0/2, 1/3, 4/6, 5/7, 8/10, 9/11, 12/14, 13/15. R1/R2 always selects the lower number, so the current checks are not correct as e.g. 2/4 could be selected as a pair. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: handle privileged instructions via flagsDavid Hildenbrand
Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: check for AFP-register, BFP and DFP data exceptionsDavid Hildenbrand
With the annotated functions, we can now easily check this at a central place. DXC 1 is to be injected if an AFP register is used (for a HFP AND FPS instruction) when AFP is disabled. DXC 2 is to be injected if a BFP instruction is used when AFP is disabled. DXC 3 is to be injected if a DFP instruction is used when AFP is disabled. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: add instruction flags for floating point instructionsDavid Hildenbrand
These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: support flags for instructionsDavid Hildenbrand
Storing flags for instructions allows us to efficiently verify certain properties at a central point. Examples might later be handling if AFP is disabled in CR0, we are not in problem state, or if vector instructions are disabled in CR0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: store in the TB flags if AFP is enabledDavid Hildenbrand
We exit the TB when changing the control registers, so just like PSW bits, this should always be consistent for a TB. Using the PSW bit semantic makes things a lot easier compared to manually defining the spare, shifted bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: factor out and fix DATA exception injectionDavid Hildenbrand
The DXC is to be stored in the low core, and only in the FPC in case AFP is enabled in CR0. Stub is not required in current code, but this way we never run into problems. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x: move tcg_s390_program_interrupt() into TCG code and mark it noreturnDavid Hildenbrand
Move it into TCG-only code and provide a stub. Turn it into noreturn. As Richard noted, we currently don't log the psw.addr before restoring the state, fix that by moving (duplicating) the qemu_log_mask in the tcg/kvm handlers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04target/s390x: exception on non-aligned LPSW(E)Pavel Zbitskiy
Both LPSW and LPSWE should raise a specification exception when their operand is not doubleword aligned. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180902003322.3428-3-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x: Fence huge pages prior to 3.1Janosch Frank
As the kernel has no way of disallowing the start of a huge page backed VM, we can migrate a running huge backed VM to a host that has no huge page KVM support. Let's glue huge page support support to the 3.1 machine, so we do not migrate to a destination host that doesn't have QEMU huge page support and can stop migration if KVM doesn't indicate support. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Message-Id: <20180928093435.198573-1-frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-02target/i386: fix translation for icount modePavel Dovgalyuk
This patch fixes the checking of boundary crossing instructions. In icount mode only first instruction of the block may cross the page boundary to keep the translation deterministic. These conditions already existed, but compared the wrong variable. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Message-Id: <20180920071702.22477.43980.stgit@pasha-VirtualBox> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02hvf: drop unused variablePaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02i386: Compile CPUX86State xsave_buf only when support KVM or HVFLiran Alon
While at it, also rename var to indicate it is not used only in KVM. Reviewed-by: Nikita Leshchenko <nikita.leshchenko@oracle.com> Reviewed-by: Patrick Colp <patrick.colp@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20180914003827.124570-2-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: rename HF_SVMI_MASK to HF_GUEST_MASKPaolo Bonzini
This flag will be used for KVM's nested VMX migration; the HF_GUEST_MASK name is already used in KVM, adopt it in QEMU as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: unify masking of interruptsPaolo Bonzini
Interrupt handling depends on various flags in env->hflags or env->hflags2, and the exact detail were not exactly replicated between x86_cpu_has_work and x86_cpu_exec_interrupt. Create a new function that extracts the highest-priority non-masked interrupt, and use it in both functions. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move x86_64_hregs to DisasContextEmilio G. Cota
And convert it to a bool to use an existing hole in the struct. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_tmp1_i64 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_tmp3_i32 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_tmp2_i32 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_ptr1 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_ptr0 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_tmp4 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_tmp0 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_T1 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_T0 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_A0 to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02target/i386: move cpu_cc_srcT to DisasContextEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-02kvm: x86: Fix kvm_arch_fixup_msi_route for remap-less caseJan Kiszka
The AMD IOMMU does not (yet) support interrupt remapping. But kvm_arch_fixup_msi_route assumes that all implementations do and crashes when the AMD IOMMU is used in KVM mode. Fixes: 8b5ed7dffa1f ("intel_iommu: add support for split irqchip") Reported-by: Christopher Goldsworthy <christopher.goldsworthy@outlook.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <48ae78d8-58ec-8813-8680-6f407ea46041@siemens.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-01target/xtensa: extract gen_check_interrupts callMax Filippov
- mark instructions that affect active IRQ level; - put call for gen_check_interrupts right after the instruction translation; when FLIX is enabled it will need to appear before other exits from the TB as well; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: make rsr/wsr helpers return voidMax Filippov
Now that all logic for TB termination is extracted from rsr/wsr their return value is not used and may be dropped. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 21:26:09 +0000