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2017-07-18target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson
We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-20-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson
We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-19-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson
We do not need to form full 64-bit quantities in order to perform the move. This reduces code expansion on 64-bit hosts. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-18-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson
This enforces proper alignment and makes the register update more natural. Note that there is a more serious bug fix for fmov {DX}Rn,@(R0,Rn) to use a store instead of a load. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-17-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Merge DREG into fpr64 routinesRichard Henderson
Also add a debugging assert that we did signal illegal opc for odd double-precision registers. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-16-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Eliminate unused XREG macroRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-15-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Hoist fp register bank selectionRichard Henderson
Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-14-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-13-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Unify cpu_fregs into FREGRichard Henderson
We were treating FREG as an index and REG as a TCGv. Making FREG return a TCGv is both less confusing and a step toward cleaner banking of cpu_fregs. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-12-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Hoist register bank selectionRichard Henderson
Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-11-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Recognize common gUSA sequencesRichard Henderson
For many of the sequences produced by gcc or glibc, we can translate these as host atomic operations. Which saves the need to acquire the exclusive lock. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-8-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Handle user-space atomicsRichard Henderson
For uniprocessors, SH4 uses optimistic restartable atomic sequences. Upon an interrupt, a real kernel would simply notice magic values in the registers and reset the PC to the start of the sequence. For QEMU, we cannot do this in quite the same way. Instead, we notice the normal start of such a sequence (mov #-x,r15), and start a new TB that can be executed under cpu_exec_step_atomic. Reported-by: Bruno Haible <bruno@clisp.org> LP: https://bugs.launchpad.net/bugs/1701971 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-7-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Adjust TB_FLAG_PENDING_MOVCARichard Henderson
Don't leave an unused bit after DELAY_SLOT_MASK. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-6-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Keep env->flags cleanRichard Henderson
If we mask off any out-of-band bits before we assign to the variable, then we don't need to clean it up when reading. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-5-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Introduce TB_FLAG_ENVFLAGS_MASKRichard Henderson
We'll be putting more things into this bitmask soon. Let's have a name that covers all possible uses. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-4-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Consolidate end-of-TB testsRichard Henderson
We can fold 3 different tests within the decode loop into a more accurate computation of max_insns to start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-3-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: return result of fcmp using TCGAurelien Jarno
Since that the T bit of the SR register is mapped using a TGC global, it's better to return the value through TCG than writing it directly. It allows to declare the helpers with the flag TCG_CALL_NO_WG. Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: do not use a helper to implement fnegAurelien Jarno
There is no need to use a helper to flip one bit, just use a TCG xor instruction instead. Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: fix FPSCR cause vs flag inversionAurelien Jarno
The floating-point status/control register contains cause and flag bits. The cause bits are set to 0 before executing the instruction, while the flag bits hold the status of the exception generated after the field was last cleared. Message-Id: <20170702202814.27793-4-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: fix FPU unorderered compareAurelien Jarno
In case of unordered compare, the fcmp instructions should either trigger and invalid exception (if enabled) or set T=0. The existing code left it unchanged. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible <bruno@clisp.org> Message-Id: <20170702202814.27793-3-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: do not check for PR bit for fabs instructionAurelien Jarno
The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible <bruno@clisp.org> Message-Id: <20170702202814.27793-2-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170718' into ↵Peter Maydell
staging s390: add z14 cpu model - add a CPU model for the IBM z14 which was announced on July 17th 2017 - update linux headers to 4.13-rc0 to get a fix for an ioctl definition # gpg: Signature made Tue 18 Jul 2017 09:56:24 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20170718: s390x/cpumodel: z14 cpu models linux header sync against v4.13-rc1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170717' into stagingPeter Maydell
Queued s390x tcg patches, v2 # gpg: Signature made Mon 17 Jul 2017 22:22:23 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-s390-20170717: target/s390x: Fix risbg handling target/s390x: Allow to enable "idtes" feature for TCG target/s390x: Mark ETF3 and ETF3_ENH facilities as available target/s390x: Implement TRTR target/s390x: Implement SRSTU target/s390x: Tidy SRST target/s390x: Implement CONVERT UNICODE insns target/s390x: Implement CSST Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86 and machine queue, 2017-07-17 # gpg: Signature made Mon 17 Jul 2017 19:46:14 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: qmp: Include parent type on 'qom-list-types' output qmp: Include 'abstract' field on 'qom-list-types' output tests: Simplify abstract-interfaces check with a helper i386: add Skylake-Server cpu model i386: Update comment about XSAVES on Skylake-Client i386: expose "TCGTCGTCGTCG" in the 0x40000000 CPUID leaf fw_cfg: move QOM type defines and fw_cfg types into fw_cfg.h fw_cfg: move qdev_init_nofail() from fw_cfg_init1() to callers fw_cfg: switch fw_cfg_find() to locate the fw_cfg device by type rather than path qom: Fix ambiguous path detection when ambiguous=NULL Revert "machine: Convert abstract typename on compat_props to subclass names" test-qdev-global-props: Test global property ordering qdev: fix the order compat and global properties are applied tests: Test case for object_resolve_path*() device-crash-test: Fix regexp on whitelist Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18Merge remote-tracking branch 'remotes/aurel/tags/pull-target-mips-20170717' ↵Peter Maydell
into staging Queued target/mips patches # gpg: Signature made Mon 17 Jul 2017 15:50:27 BST # gpg: using RSA key 0xBA9C78061DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-target-mips-20170717: target/mips: optimize WSBH, DSBH and DSHD mips: set CP0 Debug DExcCode for SDBBP instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20170717' into staging target-arm queue: * new model of the ARM MPS2/MPS2+ FPGA based development board * clean up DISAS_* exit conditions and fix various regressions since commits e75449a346 8a6b28c7b5 (in particular including ones which broke OP-TEE guests) * make Cortex-M3 and M4 correctly default to 8 PMSA regions # gpg: Signature made Mon 17 Jul 2017 13:43:45 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170717: MAINTAINERS: Add entries for MPS2 board hw/arm/mps2: Add ethernet hw/arm/mps2: Add SCC hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller hw/arm/mps2: Add timers hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device hw/arm/mps2: Add UARTs hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models target/arm: use DISAS_EXIT for eret handling target/arm: use gen_goto_tb for ISB handling target/arm/translate: ensure gen_goto_tb sets exit flags target/arm/translate.h: expand comment on DISAS_EXIT target/arm/translate: make DISAS_UPDATE match declared semantics include/exec/exec-all: document common exit conditions target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions qdev: support properties which don't set a default value qdev-properties.h: Explicitly set the default value for arraylen properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18s390x/cpumodel: z14 cpu modelsJason J. Herne
This patch introduces the CPU model for z14, along with all base and optional features. Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-17target/s390x: Fix risbg handlingRichard Henderson
The rotation is to the left, but extract shifts to the right. The computation of the extract parameters needs adjusting. For the entry condition, simplify 64 - rot + len <= 64 -rot + len <= 0 len <= rot Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reported-by: David Hildenbrand <david@redhat.com> Suggested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Allow to enable "idtes" feature for TCGDavid Hildenbrand
STFL bit 4 and 5 are just indications to the guest, which TLB entries an IDTE call will clear. These are performance indicators for the guest. STFL bit 4: INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation by selectively clearing TLB segment-table entries when a segment-table entry or entries are invalidated. IDTE also performs the clearing-by- ASCE operation. Unless bit 4 is one, IDTE simply purges all TLBs. Bit 3 is one if bit 4 is one. We can simply set STFL bit 4 ("idtes") and still purge the complete TLB. Purging more than advertised is never bad. E.g. Linux doesn't even care about this bit. We can optimized this later. This is helpful, as the z9 base model contains this facility. STFL bit 5 (clearing TLB region-table-entries) was never implemented on real HW, therefore we can simply ignore it for now. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170627161032.5014-1-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Mark ETF3 and ETF3_ENH facilities as availableRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Implement TRTRRichard Henderson
Drop TRT from the set of insns handled internally by EXECUTE. It's more important to adjust the existing helper to handle both TRT and TRTR. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Implement SRSTURichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Tidy SRSTRichard Henderson
Since we require all registers saved on input, read R0 from ENV instead of passing it manually. Recognize the specification exception when R0 contains incorrect data. Keep high bits of result registers unmodified when in 31 or 24-bit mode. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Implement CONVERT UNICODE insnsRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17target/s390x: Implement CSSTRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-17i386: add Skylake-Server cpu modelBoqun Feng (Intel)
Introduce Skylake-Server cpu mode which inherits the features from Skylake-Client and supports some additional features that are: AVX512, CLWB and PGPE1GB. Signed-off-by: Boqun Feng (Intel) <boqun.feng@gmail.com> Message-Id: <20170621052935.20715-1-boqun.feng@gmail.com> [ehabkost: copied comment about XSAVES from Skylake-Client] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-17i386: Update comment about XSAVES on Skylake-ClientEduardo Habkost
Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-17i386: expose "TCGTCGTCGTCG" in the 0x40000000 CPUID leafDaniel P. Berrange
Currently when running KVM, we expose "KVMKVMKVM\0\0\0" in the 0x40000000 CPUID leaf. Other hypervisors (VMWare, HyperV, Xen, BHyve) all do the same thing, which leaves TCG as the odd one out. The CPUID signature is used by software to detect which virtual environment they are running in and (potentially) change behaviour in certain ways. For example, systemd supports a ConditionVirtualization= setting in unit files. The virt-what command can also report the virt type it is running on Currently both these apps have to resort to custom hacks like looking for 'fw-cfg' entry in the /proc/device-tree file to identify TCG. This change thus proposes a signature "TCGTCGTCGTCG" to be reported when running under TCG. To hide this, the -cpu option tcg-cpuid=off can be used. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <20170509132736.10071-3-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-17target/mips: optimize WSBH, DSBH and DSHDAurelien Jarno
Use the same mask to avoid having to load two different constants. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-17mips: set CP0 Debug DExcCode for SDBBP instructionPavel Dovgalyuk
This patch fixes setting DExcCode field of CP0 Debug register when SDBBP instruction is executed. According to EJTAG specification, this field must be set to the value 9 (Bp). Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-id: 20170502120350.3368.92338.stgit@PASHA-ISP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-17target/arm: use DISAS_EXIT for eret handlingAlex Bennée
Previously DISAS_JUMP did ensure this but with the optimisation of 8a6b28c7 (optimize indirect branches) we might not leave the loop. This means if any pending interrupts are cleared by changing IRQ flags we might never get around to servicing them. You usually notice this by seeing the lookup_tb_ptr() helper gainfully chaining TBs together while cpu->interrupt_request remains high and the exit_request has not been set. This breaks amongst other things the OPTEE test suite which executes an eret from the secure world after a non-secure world IRQ has gone pending which then never gets serviced. Instead of using the previously implied semantics of DISAS_JUMP we use DISAS_EXIT which will always exit the run-loop. CC: Etienne Carriere <etienne.carriere@linaro.org> CC: Joakim Bech <joakim.bech@linaro.org> CC: Jaroslaw Pelczar <j.pelczar@samsung.com> CC: Peter Maydell <peter.maydell@linaro.org> CC: Emilio G. Cota <cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm: use gen_goto_tb for ISB handlingAlex Bennée
While an ISB will ensure any raised IRQs happen on the next instruction it doesn't cause any to get raised by itself. We can therefore use a simple tb exit for ISB instructions and rely on the exit_request check at the top of each TB to deal with exiting if needed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm/translate: ensure gen_goto_tb sets exit flagsAlex Bennée
As the gen_goto_tb function can do both static and dynamic jumps it should also set the is_jmp field. This matches the behaviour of the a64 code. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-5-alex.bennee@linaro.org [tweak to multiline comment formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm/translate.h: expand comment on DISAS_EXITAlex Bennée
We already have an exit condition, DISAS_UPDATE which will exit the run-loop. Expand on the difference with DISAS_EXIT in the comments. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm/translate: make DISAS_UPDATE match declared semanticsAlex Bennée
DISAS_UPDATE should be used when the wider CPU state other than just the PC has been updated and we should therefore exit the TCG runtime and return to the main execution loop rather assuming DISAS_JUMP would do that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm: Make Cortex-M3 and M4 default to 8 PMSA regionsPeter Maydell
The Cortex-M3 and M4 CPUs always have 8 PMSA MPU regions (this isn't a configurable option for the hardware). Make the default value of the pmsav7-dregion property be set per-cpu, so we don't need to have every user of these CPUs set it manually. (The existing default of 16 is correct for the other PMSAv7 core, the Cortex-R5.) This fixes a bug where we were creating the M3 and M4 with too many regions; most guest software would not notice or care, though, since it would just not use the registers associated with the unexpected extra regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1499788408-10096-4-git-send-email-peter.maydell@linaro.org
2017-07-17target/ppc: fix CPU hotplug when radix is enabled (TCG)Cédric Le Goater
But when a guest initializes radix mode, it issues a H_REGISTER_PROC_TBL to update the LPCR of all CPUs. Hot-plugged CPUs inherit from the same setting under KVM but not under TCG. So, Let's check for radix and update the default LPCR to keep new CPUs in sync. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-17pseries: Allow HPT resizing with KVMDavid Gibson
So far, qemu implements the PAPR Hash Page Table (HPT) resizing extension with TCG. The same implementation will work with KVM PR, but we don't currently allow that. For KVM HV we can only implement resizing with the assistance of the host kernel, which needs a new capability and ioctl()s. This patch adds support for testing the new KVM capability and implementing the resize in terms of KVM facilities when necessary. If we're running on a kernel which doesn't have the new capability flag at all, we fall back to testing for PR vs. HV KVM using the same hack that we already use in a number of places for older kernels. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-17pseries: Implement HPT resizingDavid Gibson
This patch implements hypercalls allowing a PAPR guest to resize its own hash page table. This will eventually allow for more flexible memory hotplug. The implementation is partially asynchronous, handled in a special thread running the hpt_prepare_thread() function. The state of a pending resize is stored in SPAPR_MACHINE->pending_hpt. The H_RESIZE_HPT_PREPARE hypercall will kick off creation of a new HPT, or, if one is already in progress, monitor it for completion. If there is an existing HPT resize in progress that doesn't match the size specified in the call, it will cancel it, replacing it with a new one matching the given size. The H_RESIZE_HPT_COMMIT completes transition to a resized HPT, and can only be called successfully once H_RESIZE_HPT_PREPARE has successfully completed initialization of a new HPT. The guest must ensure that there are no concurrent accesses to the existing HPT while this is called (this effectively means stop_machine() for Linux guests). For now H_RESIZE_HPT_COMMIT goes through the whole old HPT, rehashing each HPTE into the new HPT. This can have quite high latency, but it seems to be of the order of typical migration downtime latencies for HPTs of size up to ~2GiB (which would be used in a 256GiB guest). In future we probably want to move more of the rehashing to the "prepare" phase, by having H_ENTER and other hcalls update both current and pending HPTs. That's a project for another day, but should be possible without any changes to the guest interface. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-17pseries: Stubs for HPT resizingDavid Gibson
This introduces stub implementations of the H_RESIZE_HPT_PREPARE and H_RESIZE_HPT_COMMIT hypercalls which we hope to add in a PAPR extension to allow run time resizing of a guest's hash page table. It also adds a new machine property for controlling whether this new facility is available. For now we only allow resizing with TCG, allowing it with KVM will require kernel changes as well. Finally, it adds a new string to the hypertas property in the device tree, advertising to the guest the availability of the HPT resizing hypercalls. This is a tentative suggested value, and would need to be standardized by PAPR before being merged. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com>
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