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2019-10-28target/xtensa: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/sparc: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/riscv: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28target/alpha: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/m68k: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/hppa: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/i386: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/sh4: fetch code with translator_ldEmilio G. Cota
There is a small wrinkle with the gUSA instruction. The translator effectively treats a (known) gUSA sequence as a single instruction. For the purposes of the plugin we end up with a long multi-instruction qemu_plugin_insn. If the known sequence isn't detected we shall never run this translation anyway. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/ppc: fetch code with translator_ldEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-10-28target/arm: fetch code with translator_ldEmilio G. Cota
Now the arm_ld*_code functions are only used at translate time we can just pass down to translator_ld functions. Signed-off-by: Emilio G. Cota <cota@braap.org> [AJB: convert from plugin_insn_append to translator_ld] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28cputlb: ensure _cmmu helper functions follow the naming standardAlex Bennée
We document this in docs/devel/load-stores.rst so lets follow it. The 32 bit and 64 bit access functions have historically not included the sign so we leave those as is. We also introduce some signed helpers which are used for loading immediate values in the translator. Fixes: 282dffc8 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20191021150910.23216-1-alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-26i386: implement IGNNEPaolo Bonzini
Change the handling of port F0h writes and FPU exceptions to implement IGNNE. The implementation mixes a bit what the chipset and processor do in real hardware, but the effect is the same as what happens with actual FERR# and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26target/i386: introduce cpu_set_fpusPaolo Bonzini
In the next patch, this will provide a hook to detect clearing of FSW.ES. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26target/i386: move FERR handling to target/i386Paolo Bonzini
Move it out of pc.c since it is strictly tied to TCG. This is almost exclusively code movement, the next patch will implement IGNNE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26core: replace getpagesize() with qemu_real_host_page_sizeWei Yang
There are three page size in qemu: real host page size host page size target page size All of them have dedicate variable to represent. For the last two, we use the same form in the whole qemu project, while for the first one we use two forms: qemu_real_host_page_size and getpagesize(). qemu_real_host_page_size is defined to be a replacement of getpagesize(), so let it serve the role. [Note] Not fully tested for some arch or device. Signed-off-by: Wei Yang <richardw.yang@linux.intel.com> Message-Id: <20191013021145.16011-3-richardw.yang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-26Merge commit 'df84f17' into HEADPaolo Bonzini
This merge fixes a semantic conflict with the trivial tree. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-25target/mips: Refactor handling of vector compare 'less than' (signed) ↵Filip Bozuta
instructions Remove unnecessary argument and provide separate function for each instruction. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571837825-24438-3-git-send-email-Filip.Bozuta@rt-rk.com>
2019-10-25target/mips: Refactor handling of vector compare 'equal' instructionsFilip Bozuta
Remove unnecessary argument and provide separate function for each instruction. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571837825-24438-2-git-send-email-Filip.Bozuta@rt-rk.com>
2019-10-25target/mips: Demacro LMI decoderAleksandar Markovic
This makes searches for instances of opcode usages easier. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-15-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Message-Id: <1571826227-10583-13-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Message-Id: <1571826227-10583-12-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: Clean up op_helper.cAleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-25target/mips: Clean up helper.cAleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Cc: Markus Armbruster <armbru@redhat.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-10-24target/arm: Rely on hflags correct in cpu_get_tb_cpu_stateRichard Henderson
This is the payoff. From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Rebuild hflags for M-profileRichard Henderson
Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Rebuild hflags at Xscale SCTLR writesRichard Henderson
Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Rebuild hflags at CPSR writesRichard Henderson
Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Rebuild hflags at MSR writesRichard Henderson
Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Rebuild hflags at EL changesRichard Henderson
Begin setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32})Richard Henderson
This functions are given the mode and el state of the cpu and writes the computed value to env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Hoist store to cs_base in cpu_get_tb_cpu_stateRichard Henderson
By performing this store early, we avoid having to save and restore the register holding the address around any function calls. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split out arm_mmu_idx_elRichard Henderson
Avoid calling arm_current_el() twice. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Add arm_rebuild_hflagsRichard Henderson
This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Hoist computation of TBFLAG_A32.VFPENRichard Henderson
There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_stateRichard Henderson
Hoist the variable load for PSTATE into the existing test vs is_a64. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_stateRichard Henderson
We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split out rebuild_hflags_aprofileRichard Henderson
Create a function to compute the values of the TBFLAG_ANY bits that will be cached, and are used by A-profile. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split out rebuild_hflags_a32Richard Henderson
Currently a trivial wrapper for rebuild_hflags_common_32. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_stateRichard Henderson
Hoist the computation of some TBFLAG_A32 bits that only apply to M-profile under a single test for ARM_FEATURE_M. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split out rebuild_hflags_m32Richard Henderson
Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by M-profile. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split arm_cpu_data_is_big_endianRichard Henderson
Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and rebuild_hflags_a64 instead of rebuild_hflags_common, where we do not need to re-test is_a64() nor re-compute the various inputs. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split out rebuild_hflags_common_32Richard Henderson
Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by all profiles. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24target/arm: Split out rebuild_hflags_a64Richard Henderson
Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Note that not all BTI related flags are cached, so we have to test the BTI feature twice -- once for those bits moved out to rebuild_hflags_a64 and once for those bits that remain in cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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