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AgeCommit message (Expand)Author
2022-05-26target/ppc: Implemented xvi*ger* instructionsLucas Mateus Castro (alqotel)
2022-05-26target/ppc: Implement xxm[tf]acc and xxsetacczLucas Mateus Castro (alqotel)
2022-05-26target/ppc: Implement lwsync with weaker memory orderingNicholas Piggin
2022-05-26target/ppc: Fix eieio memory ordering semanticsNicholas Piggin
2022-05-26target/ppc: declare vmsumsh[ms] helper with call flagsMatheus Ferst
2022-05-26target/ppc: declare vmsumuh[ms] helper with call flagsMatheus Ferst
2022-05-26target/ppc: declare vmsum[um]bm helpers with call flagsMatheus Ferst
2022-05-26target/ppc: introduce do_va_helperMatheus Ferst
2022-05-26target/ppc: declare xxextractuw and xxinsertw helpers with call flagsMatheus Ferst
2022-05-26target/ppc: declare xvxsigsp helper with call flagsMatheus Ferst
2022-05-26target/ppc: declare xscvspdpn helper with call flagsMatheus Ferst
2022-05-26target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helperMatheus Ferst
2022-05-26target/ppc: use TCG_CALL_NO_RWG in VSX helpers without envMatheus Ferst
2022-05-26target/ppc: use TCG_CALL_NO_RWG in BCD helpersMatheus Ferst
2022-05-26target/ppc: use TCG_CALL_NO_RWG in vector helpers without envMatheus Ferst
2022-05-26target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWGMatheus Ferst
2022-05-26target/ppc: Rename sfprf to sfifprf where it's also used as set fi flagVíctor Colombo
2022-05-26target/ppc: Fix FPSCR.FI changing in float_overflow_excp()Víctor Colombo
2022-05-26target/ppc: Fix FPSCR.FI bit being cleared when it shouldn'tVíctor Colombo
2022-05-26target/ppc: Fix tlbieLeandro Lupori
2022-05-25Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
2022-05-25i386: Hyper-V Direct TLB flush hypercallVitaly Kuznetsov
2022-05-25i386: Hyper-V Support extended GVA ranges for TLB flush hypercallsVitaly Kuznetsov
2022-05-25i386: Hyper-V XMM fast hypercall input featureVitaly Kuznetsov
2022-05-25i386: Hyper-V Enlightened MSR bitmap featureVitaly Kuznetsov
2022-05-25i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURESVitaly Kuznetsov
2022-05-25target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable hostMaciej S. Szmigiero
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI
2022-05-24target/riscv: FP extension requirementsTsukasa OI
2022-05-24target/riscv: Change "G" expansionTsukasa OI
2022-05-24target/riscv: Disable "G" by defaultTsukasa OI
2022-05-24target/riscv: Fix coding style on "G" expansionTsukasa OI
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI
2022-05-24target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD
2022-05-24target/riscv: Fix VS mode hypervisor CSR accessDylan Reid
2022-05-23target/i386: Remove LBREn bit check when access Arch LBR MSRsYang Weijiang
2022-05-19target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson
2022-05-19target/arm: Enable FEAT_HCX for -cpu maxRichard Henderson
2022-05-19target/arm: Fix PAuth keys access checks for disabled SEL2Florian Lugou
2022-05-19target/arm: Make number of counters in PMCR follow the CPUPeter Maydell
2022-05-19target/arm/helper.c: Delete stray obsolete commentPeter Maydell
2022-05-19Fix aarch64 debug register names.Chris Howard
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell