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2022-04-22Merge tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmayd...Richard Henderson
2022-04-22target/arm: Use tcg_constant_i32 in translate.hRichard Henderson
2022-04-22target/arm: Use tcg_constant in translate-vfp.cRichard Henderson
2022-04-22target/arm: Use smin/smax for do_sat_addsub_32Richard Henderson
2022-04-22target/arm: Use tcg_constant in translate-neon.cRichard Henderson
2022-04-22target/arm: Use tcg_constant in translate-m-nocp.cRichard Henderson
2022-04-22target/arm: Simplify aa32 DISAS_WFIRichard Henderson
2022-04-22target/arm: Simplify gen_sarRichard Henderson
2022-04-22target/arm: Simplify GEN_SHIFT in translate.cRichard Henderson
2022-04-22target/arm: Split out gen_rebuild_hflagsRichard Henderson
2022-04-22target/arm: Split out set_btype_rawRichard Henderson
2022-04-22target/arm: Remove fpexc32_accessRichard Henderson
2022-04-22target/arm: Change CPUArchState.thumb to boolRichard Henderson
2022-04-22target/arm: Change DisasContext.thumb to boolRichard Henderson
2022-04-22target/arm: Extend store_cpu_offset to take field sizeRichard Henderson
2022-04-22target/arm: Change CPUArchState.aarch64 to boolRichard Henderson
2022-04-22target/arm: Change DisasContext.aarch64 to boolRichard Henderson
2022-04-22target/arm: Update SCTLR bits to ARMv9.2Richard Henderson
2022-04-22target/arm: Update SCR_EL3 bits to ARMv8.8Richard Henderson
2022-04-22target/arm: Update ISAR fields for ARMv8.8Richard Henderson
2022-04-22target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2Peter Maydell
2022-04-21Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:alistair23/qemu into...Richard Henderson
2022-04-22target/riscv: cpu: Enable native debug featureBin Meng
2022-04-22target/riscv: machine: Add debug state descriptionBin Meng
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng
2022-04-22target/riscv: debug: Implement debug related TCGCPUOpsBin Meng
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang
2022-04-22target/riscv/pmp: fix NAPOT range computation overflowNicolas Pitre
2022-04-22target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson
2022-04-22target/riscv: fix start byte for vmv<nf>r.v when vstart != 0Weiwei Li
2022-04-22target/riscv: Add isa extenstion strings to the device treeAtish Patra
2022-04-22target/riscv: misa to ISA string conversion fixTsukasa OI
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
2022-04-22target/riscv: cpu: Fixup indentationAlistair Francis
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Add support for mconfigptrAtish Patra
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra
2022-04-22target/riscv: Add the privileged spec version 1.12.0Atish Patra
2022-04-22target/riscv: Define simpler privileged spec version numberingAtish Patra
2022-04-21Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
2022-04-21target/rx: update PC correctly in wait instructionTomoaki Kawada
2022-04-21target/rx: set PSW.I when executing wait instructionTomoaki Kawada
2022-04-21target/rx: Swap stack pointers on clrpsw/setpsw instructionRichard Henderson
2022-04-21target/rx: Move DISAS_UPDATE check for write to PSWRichard Henderson
2022-04-21target/rx: Store PSW.U in tb->flagsRichard Henderson