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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2022-04-22
Merge tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmayd...
Richard Henderson
2022-04-22
target/arm: Use tcg_constant_i32 in translate.h
Richard Henderson
2022-04-22
target/arm: Use tcg_constant in translate-vfp.c
Richard Henderson
2022-04-22
target/arm: Use smin/smax for do_sat_addsub_32
Richard Henderson
2022-04-22
target/arm: Use tcg_constant in translate-neon.c
Richard Henderson
2022-04-22
target/arm: Use tcg_constant in translate-m-nocp.c
Richard Henderson
2022-04-22
target/arm: Simplify aa32 DISAS_WFI
Richard Henderson
2022-04-22
target/arm: Simplify gen_sar
Richard Henderson
2022-04-22
target/arm: Simplify GEN_SHIFT in translate.c
Richard Henderson
2022-04-22
target/arm: Split out gen_rebuild_hflags
Richard Henderson
2022-04-22
target/arm: Split out set_btype_raw
Richard Henderson
2022-04-22
target/arm: Remove fpexc32_access
Richard Henderson
2022-04-22
target/arm: Change CPUArchState.thumb to bool
Richard Henderson
2022-04-22
target/arm: Change DisasContext.thumb to bool
Richard Henderson
2022-04-22
target/arm: Extend store_cpu_offset to take field size
Richard Henderson
2022-04-22
target/arm: Change CPUArchState.aarch64 to bool
Richard Henderson
2022-04-22
target/arm: Change DisasContext.aarch64 to bool
Richard Henderson
2022-04-22
target/arm: Update SCTLR bits to ARMv9.2
Richard Henderson
2022-04-22
target/arm: Update SCR_EL3 bits to ARMv8.8
Richard Henderson
2022-04-22
target/arm: Update ISAR fields for ARMv8.8
Richard Henderson
2022-04-22
target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
Peter Maydell
2022-04-21
Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:alistair23/qemu into...
Richard Henderson
2022-04-22
target/riscv: cpu: Enable native debug feature
Bin Meng
2022-04-22
target/riscv: machine: Add debug state description
Bin Meng
2022-04-22
target/riscv: csr: Hook debug CSR read/write
Bin Meng
2022-04-22
target/riscv: cpu: Add a config option for native debug
Bin Meng
2022-04-22
target/riscv: debug: Implement debug related TCGCPUOps
Bin Meng
2022-04-22
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
Frank Chang
2022-04-22
target/riscv/pmp: fix NAPOT range computation overflow
Nicolas Pitre
2022-04-22
target/riscv: Use cpu_loop_exit_restore directly from mmu faults
Richard Henderson
2022-04-22
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
Weiwei Li
2022-04-22
target/riscv: Add isa extenstion strings to the device tree
Atish Patra
2022-04-22
target/riscv: misa to ISA string conversion fix
Tsukasa OI
2022-04-22
target/riscv: optimize helper for vmv<nr>r.v
Weiwei Li
2022-04-22
target/riscv: optimize condition assign for scale < 0
Weiwei Li
2022-04-22
target/riscv: Add initial support for the Sdtrig extension
Bin Meng
2022-04-22
target/riscv: Allow software access to MIP SEIP
Alistair Francis
2022-04-22
target/riscv: cpu: Fixup indentation
Alistair Francis
2022-04-22
target/riscv: Enable privileged spec version 1.12
Atish Patra
2022-04-22
target/riscv: Add *envcfg* CSRs support
Atish Patra
2022-04-22
target/riscv: Add support for mconfigptr
Atish Patra
2022-04-22
target/riscv: Introduce privilege version field in the CSR ops.
Atish Patra
2022-04-22
target/riscv: Add the privileged spec version 1.12.0
Atish Patra
2022-04-22
target/riscv: Define simpler privileged spec version numbering
Atish Patra
2022-04-21
Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu into staging
Richard Henderson
2022-04-21
target/rx: update PC correctly in wait instruction
Tomoaki Kawada
2022-04-21
target/rx: set PSW.I when executing wait instruction
Tomoaki Kawada
2022-04-21
target/rx: Swap stack pointers on clrpsw/setpsw instruction
Richard Henderson
2022-04-21
target/rx: Move DISAS_UPDATE check for write to PSW
Richard Henderson
2022-04-21
target/rx: Store PSW.U in tb->flags
Richard Henderson
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