slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-03-10	s390x: ipl: Consolidate iplb validity check into one function	Janosch Frank
2020-03-05	RISC-V: Add a missing "," in riscv_excp_names	Palmer Dabbelt
2020-03-05	target/arm: Clean address for DC ZVA	Richard Henderson
2020-03-05	target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva	Richard Henderson
2020-03-05	target/arm: Move helper_dc_zva to helper-a64.c	Richard Henderson
2020-03-05	target/arm: Apply TBI to ESR_ELx in helper_exception_return	Richard Henderson
2020-03-05	target/arm: Introduce core_to_aa64_mmu_idx	Richard Henderson
2020-03-05	target/arm: Optimize cpu_mmu_index	Richard Henderson
2020-03-05	target/arm: Replicate TBI/TBID bits for single range regimes	Richard Henderson
2020-03-05	target/arm: Honor the HCR_EL2.TTLB bit	Richard Henderson
2020-03-05	target/arm: Honor the HCR_EL2.TPU bit	Richard Henderson
2020-03-05	target/arm: Honor the HCR_EL2.TPCP bit	Richard Henderson
2020-03-05	target/arm: Honor the HCR_EL2.TACR bit	Richard Henderson
2020-03-05	target/arm: Honor the HCR_EL2.TSW bit	Richard Henderson
2020-03-05	target/arm: Honor the HCR_EL2.{TVM,TRVM} bits	Richard Henderson
2020-03-05	target/arm: Improve masking in arm_hcr_el2_eff	Richard Henderson
2020-03-05	target/arm: Remove EL2 and EL3 setup from user-only	Richard Henderson
2020-03-05	target/arm: Disable has_el2 and has_el3 for user-only	Richard Henderson
2020-03-05	target/arm: Add HCR_EL2 bit definitions from ARMv8.6	Richard Henderson
2020-03-05	target/arm: Improve masking of HCR/HCR2 RES0 bits	Richard Henderson
2020-03-05	target/arm: Implement (trivially) ARMv8.2-TTCNP	Peter Maydell
2020-03-03	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...	Peter Maydell
2020-02-28	target/arm: Implement ARMv8.3-CCIDX	Peter Maydell
2020-02-28	target/arm: Implement v8.4-RCPC	Peter Maydell
2020-02-28	target/arm: Implement v8.3-RCPC	Peter Maydell
2020-02-28	target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0	Peter Maydell
2020-02-28	target/arm: Split VMINMAXNM decode	Richard Henderson
2020-02-28	target/arm: Split VFM decode	Richard Henderson
2020-02-28	target/arm: Add formats for some vfp 2 and 3-register insns	Richard Henderson
2020-02-28	target/arm: Remove ARM_FEATURE_VFP*	Richard Henderson
2020-02-28	target/arm: Move the vfp decodetree calls next to the base isa	Richard Henderson
2020-02-28	target/arm: Move VLLDM and VLSTM to vfp.decode	Richard Henderson
2020-02-28	target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn	Richard Henderson
2020-02-28	target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac	Richard Henderson
2020-02-28	target/arm: Add missing checks for fpsp_v2	Richard Henderson
2020-02-28	target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3	Richard Henderson
2020-02-28	target/arm: Perform fpdp_v2 check first	Richard Henderson
2020-02-28	target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp	Richard Henderson
2020-02-28	target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}	Richard Henderson
2020-02-28	target/arm: Rename isar_feature_aa32_fpdp_v2	Richard Henderson
2020-02-28	target/arm: Add isar_feature_aa32_vfp_simd	Richard Henderson
2020-02-28	target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn	Richard Henderson
2020-02-27	target/riscv: Emulate TIME CSRs for privileged mode	Anup Patel
2020-02-27	target/riscv: Allow enabling the Hypervisor extension	Alistair Francis
2020-02-27	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	Alistair Francis
2020-02-27	target/riscv: Add support for the 32-bit MSTATUSH CSR	Alistair Francis
2020-02-27	target/riscv: Set htval and mtval2 on execptions	Alistair Francis
2020-02-27	target/riscv: Raise the new execptions when 2nd stage translation fails	Alistair Francis
2020-02-27	target/riscv: Implement second stage MMU	Alistair Francis
2020-02-27	target/riscv: Allow specifying MMU stage	Alistair Francis