slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-11-03	Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core	Taylor Simpson
2021-11-03	Hexagon HVX (target/hexagon) README	Taylor Simpson
2021-10-29	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in...	Richard Henderson
2021-10-29	target/i386: Remove core-capability in Snowridge CPU model	Chenyi Qiang
2021-10-29	Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...	Richard Henderson
2021-10-29	Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into staging	Richard Henderson
2021-10-29	target/riscv: change the api for RVF/RVD fmin/fmax	Chih-Min Chao
2021-10-29	target/riscv: remove force HS exception	Jose Martins
2021-10-29	target/riscv: fix VS interrupts forwarding to HS	Jose Martins
2021-10-28	Hexagon (target/hexagon) put writes to USR into temp until commit	Taylor Simpson
2021-10-28	Hexagon (target/hexagon) more tcg_constant_*	Taylor Simpson
2021-10-28	target/riscv: Allow experimental J-ext to be turned on	Alexey Baturo
2021-10-28	target/riscv: Implement address masking functions required for RISC-V Pointer...	Anatoly Parshintsev
2021-10-28	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...	Alexey Baturo
2021-10-28	target/riscv: Print new PM CSRs in QEMU logs	Alexey Baturo
2021-10-28	target/riscv: Add J extension state description	Alexey Baturo
2021-10-28	target/riscv: Support CSRs required for RISC-V PM extension except for the h-...	Alexey Baturo
2021-10-28	target/riscv: Add CSR defines for RISC-V PM extension	Alexey Baturo
2021-10-28	target/riscv: Add J-extension into RISC-V	Alexey Baturo
2021-10-27	host-utils: add 128-bit quotient support to divu128/divs128	Luis Pires
2021-10-27	host-utils: move checks out of divu128/divs128	Luis Pires
2021-10-23	Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...	Richard Henderson
2021-10-22	disas/nios2: Simplify endianess conversion	Philippe Mathieu-Daudé
2021-10-22	target/riscv: Compute mstatus.sd on demand	Richard Henderson
2021-10-22	target/riscv: Use riscv_csrrw_debug for cpu_dump	Richard Henderson
2021-10-22	target/riscv: Use gen_shift*_per_ol for RVB, RVI	Richard Henderson
2021-10-22	target/riscv: Use gen_unary_per_ol for RVB	Richard Henderson
2021-10-22	target/riscv: Adjust trans_rev8_32 for riscv64	Richard Henderson
2021-10-22	target/riscv: Use gen_arith_per_ol for RVM	Richard Henderson
2021-10-22	target/riscv: Replace DisasContext.w with DisasContext.ol	Richard Henderson
2021-10-22	target/riscv: Replace is_32bit with get_xl/get_xlen	Richard Henderson
2021-10-22	target/riscv: Properly check SEW in amo_op	Richard Henderson
2021-10-22	target/riscv: Use REQUIRE_64BIT in amo_check64	Richard Henderson
2021-10-22	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	Richard Henderson
2021-10-22	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	Richard Henderson
2021-10-22	target/riscv: Split misa.mxl and misa.ext	Richard Henderson
2021-10-22	target/riscv: Create RISCVMXL enumeration	Richard Henderson
2021-10-22	target/riscv: Move cpu_get_tb_cpu_state out of line	Richard Henderson
2021-10-22	target/riscv: Organise the CPU properties	Alistair Francis
2021-10-22	target/riscv: Remove some unused macros	Alistair Francis
2021-10-22	target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh	Frank Chang
2021-10-22	target/riscv: Fix orc.b implementation	Philipp Tomsich
2021-10-22	target/riscv: line up all of the registers in the info register dump	Travis Geiselbrecht
2021-10-22	target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v	Frank Chang
2021-10-21	target/ppc: adding user read/write functions for PMCs	Daniel Henrique Barboza
2021-10-21	target/ppc: add user read/write functions for MMCR2	Daniel Henrique Barboza
2021-10-21	target/ppc: add user read/write functions for MMCR0	Gustavo Romero
2021-10-21	target/ppc: add MMCR0 PMCC bits to hflags	Daniel Henrique Barboza
2021-10-21	target/ppc: Filter mtmsr[d] input before setting MSR	Matheus Ferst
2021-10-21	target/ppc: Fix XER access in monitor	Matheus Ferst