slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-02-16	target/riscv: add support for svpbmt extension	Weiwei Li
2022-02-16	target/riscv: add support for svinval extension	Weiwei Li
2022-02-16	target/riscv: add support for svnapot extension	Weiwei Li
2022-02-16	target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE	Weiwei Li
2022-02-16	target/riscv: Ignore reserved bits in PTE for RV64	Guo Ren
2022-02-16	target/riscv: Allow users to force enable AIA CSRs in HART	Anup Patel
2022-02-16	target/riscv: Implement AIA IMSIC interface CSRs	Anup Patel
2022-02-16	target/riscv: Implement AIA xiselect and xireg CSRs	Anup Patel
2022-02-16	target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs	Anup Patel
2022-02-16	target/riscv: Implement AIA interrupt filtering CSRs	Anup Patel
2022-02-16	target/riscv: Implement AIA hvictl and hviprioX CSRs	Anup Patel
2022-02-16	target/riscv: Implement AIA CSRs for 64 local interrupts on RV32	Anup Patel
2022-02-16	target/riscv: Implement AIA local interrupt priorities	Anup Patel
2022-02-16	target/riscv: Allow AIA device emulation to set ireg rmw callback	Anup Patel
2022-02-16	target/riscv: Add defines for AIA CSRs	Anup Patel
2022-02-16	target/riscv: Add AIA cpu feature	Anup Patel
2022-02-16	target/riscv: Allow setting CPU feature from machine/device emulation	Anup Patel
2022-02-16	target/riscv: Improve delivery of guest external interrupts	Anup Patel
2022-02-16	target/riscv: Implement hgeie and hgeip CSRs	Anup Patel
2022-02-16	target/riscv: Implement SGEIP bit in hip and hie CSRs	Anup Patel
2022-02-16	target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode	Anup Patel
2022-02-16	target/riscv: Fix vill field write in vtype	LIU Zhiwei
2022-02-16	target/riscv: Add XVentanaCondOps custom extension	Philipp Tomsich
2022-02-16	target/riscv: iterate over a table of decoders	Philipp Tomsich
2022-02-16	target/riscv: access cfg structure through DisasContext	Philipp Tomsich
2022-02-16	target/riscv: access configuration through cfg_ptr in DisasContext	Philipp Tomsich
2022-02-16	target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr	Philipp Tomsich
2022-02-16	target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...	Philipp Tomsich
2022-02-16	target/riscv: correct "code should not be reached" for x-rv128	Frédéric Pétrot
2022-02-13	Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220210' into s...	Peter Maydell
2022-02-09	target/i386: use CPU_LOG_INT for IRQ servicing	Alex Bennée
2022-02-09	target/ppc: Change VSX instructions behavior to fill with zeros	Víctor Colombo
2022-02-09	target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail	Fabiano Rosas
2022-02-09	target/ppc: Assert if MSR bits differ from msr_mask during exceptions	Fabiano Rosas
2022-02-09	target/ppc: powerpc_excp: Move common code to the caller function	Fabiano Rosas
2022-02-09	target/ppc: Remove powerpc_excp_legacy	Fabiano Rosas
2022-02-09	target/ppc: 7xx: Set SRRs directly in exception code	Fabiano Rosas
2022-02-09	target/ppc: 7xx: Software TLB cleanup	Fabiano Rosas
2022-02-09	target/ppc: 7xx: System Reset cleanup	Fabiano Rosas
2022-02-09	target/ppc: 7xx: System Call exception cleanup	Fabiano Rosas
2022-02-09	target/ppc: 7xx: Program exception cleanup	Fabiano Rosas
2022-02-09	target/ppc: 7xx: External interrupt cleanup	Fabiano Rosas
2022-02-09	target/ppc: 7xx: Machine Check exception cleanup	Fabiano Rosas
2022-02-09	target/ppc: Simplify powerpc_excp_7xx	Fabiano Rosas
2022-02-09	target/ppc: Introduce powerpc_excp_7xx	Fabiano Rosas
2022-02-09	target/ppc: Merge 7x5 and 7x0 exception model IDs	Fabiano Rosas
2022-02-09	target/ppc: 6xx: Set SRRs directly in exception code	Fabiano Rosas
2022-02-09	target/ppc: 6xx: Software TLB exceptions cleanup	Fabiano Rosas
2022-02-09	target/ppc: 6xx: System Reset interrupt cleanup	Fabiano Rosas
2022-02-09	target/ppc: 6xx: System Call exception cleanup	Fabiano Rosas