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2018-02-09s390x/flic: factor out injection of floating interruptsDavid Hildenbrand
Let the flic device handle it internally. This will allow us to later on store floating interrupts in the flic for the TCG case. This now also simplifies kvm.c. All that's left is the fallback interface for floating interrupts, which is now triggered directly via the flic in case anything goes wrong. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: simplify machine check handlingDavid Hildenbrand
We currently only support CRW machine checks. This is a preparation for real floating interrupt support. Get rid of the queue and handle it via the bit INTERRUPT_MCHK. We don't rename it for now, as it will be soon gone (when moving crw machine checks into the flic). Please note that this is the same way also KVM handles it: only one instance of a machine check can be pending at a time. So no need for a queue. While at it, make sure we try to deliver only if env->cregs[14] actually indicates that CRWs are accepted. Drop two unused defines on the way (we already have PSW_MASK_...). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: deliver multiple interrupts in a rowDavid Hildenbrand
We have to consider all deliverable interrupts. We now have to take care of the special scenario, where we first inject an interrupt with a WAIT PSW, followed by a !WAIT PSW. (very unlikely but possible) Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-07Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* socket option parsing fix (Daniel) * SCSI fixes (Fam) * Readline double-free fix (Greg) * More HVF attribution fixes (Izik) * WHPX (Windows Hypervisor Platform Extensions) support (Justin) * POLLHUP handler (Klim) * ivshmem fixes (Ladi) * memfd memory backend (Marc-André) * improved error message (Marcelo) * Memory fixes (Peter Xu, Zhecheng) * Remove obsolete code and comments (Peter M.) * qdev API improvements (Philippe) * Add CONFIG_I2C switch (Thomas) # gpg: Signature made Wed 07 Feb 2018 15:24:08 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (47 commits) Add the WHPX acceleration enlightenments Introduce the WHPX impl Add the WHPX vcpu API Add the Windows Hypervisor Platform accelerator. tests/test-filter-redirector: move close() tests: use memfd in vhost-user-test vhost-user-test: make read-guest-mem setup its own qemu tests: keep compiling failing vhost-user tests Add memfd based hostmem memfd: add hugetlbsize argument memfd: add hugetlb support memfd: add error argument, instead of perror() cpus: join thread when removing a vCPU cpus: hvf: unregister thread with RCU cpus: tcg: unregister thread with RCU, fix exiting of loop on unplug cpus: dummy: unregister thread with RCU, exit loop on unplug cpus: kvm: unregister thread with RCU cpus: hax: register/unregister thread with RCU, exit loop on unplug ivshmem: Disable irqfd on device reset ivshmem: Improve MSI irqfd error handling ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # cpus.c
2018-02-07Add the WHPX acceleration enlightenmentsJustin Terry (VM)
Implements the WHPX accelerator cpu enlightenments to actually use the whpx-all accelerator on Windows platforms. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1516655269-1785-5-git-send-email-juterry@microsoft.com> [Register/unregister VCPU thread with RCU. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-07Introduce the WHPX implJustin Terry (VM)
Implements the Windows Hypervisor Platform accelerator (WHPX) target. Which acts as a hypervisor accelerator for QEMU on the Windows platform. This enables QEMU much greater speed over the emulated x86_64 path's that are taken on Windows today. 1. Adds support for vPartition management. 2. Adds support for vCPU management. 3. Adds support for MMIO/PortIO. 4. Registers the WHPX ACCEL_CLASS. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1516655269-1785-4-git-send-email-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-07arm: postpone device listener unregisterPeter Xu
It's a preparation for follow-up patch to call region_del() in memory_listener_unregister(), otherwise all device addr attached with kvm_devices_head will be reset before calling kvm_arm_set_device_addr. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20180122060244.29368-3-peterx@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-06spapr/iommu: Enable in-kernel TCE acceleration via VFIO KVM deviceAlexey Kardashevskiy
In order to enable TCE operations support in KVM, we have to inform the KVM about VFIO groups being attached to specific LIOBNs; the necessary bits are implemented already by IOMMU MR and VFIO. This defines get_attr() for the SPAPR TCE IOMMU MR which makes VFIO call the KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE ioctl and establish LIOBN-to-IOMMU link. This changes spapr_tce_set_need_vfio() to avoid TCE table reallocation if the kernel supports the TCE acceleration. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> [aw - remove unnecessary sys/ioctl.h include] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-02-05hvf: ept_emulation_fault() needs NetApp BSD attributionPaolo Bonzini
Add the BSD license there. Reported-by: Izik Eidus <izik@veertu.com> Message-Id: <20180123123639.35255-3-izik@veertu.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-05Add missing hvdos public domain attribution:Izik Eidus
hvf.c and vmx.h contain code from hvdos.c that is released as public domain: from hvdos github: https://github.com/mist64/hvdos "License See LICENSE.txt (2-clause-BSD). In order to simplify use of this code as a template, you can consider any parts from "hvdos.c" and "interface.h" as being in the public domain." Signed-off-by: Izik Eidus <izik@veertu.com> Message-Id: <20180123123639.35255-2-izik@veertu.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-31target/hppa: Implement PROBE for system modeRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Fix 32-bit operand masks for 0E FCVTRichard Henderson
We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Enable MTTCGRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement STWARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement a pause instructionRichard Henderson
This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement LDSID for system modeHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Fix commentHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Increase number of temp regsRichard Henderson
HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Only use EXCP_DTLB_MISSRichard Henderson
Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement B,GATE insnRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Add migration for the cpuRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Add system registers to gdbstubRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Optimize for flat addressing spaceRichard Henderson
Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement halt and reset instructionsHelge Deller
Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement SYNCDMA insnRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LCIRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LPARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LDWARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement P*TLB and P*TLBE insnsRichard Henderson
We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement I*TLBA and I*TLBP insnsRichard Henderson
The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Log unimplemented instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement the interval timerRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement external interruptsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement tlb_fillRichard Henderson
However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement IASQRichard Henderson
Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Avoid privilege level decrease during branchesRichard Henderson
These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Use space registers in data operationsRichard Henderson
This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement unaligned access trapRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interruptRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement rfiRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Adjust insn mask for mfctl,wRichard Henderson
While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Add control registersRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Add space registersRichard Henderson
Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement the system mask instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement mmu_idx from IA privilege levelRichard Henderson
Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Split address size from register sizeRichard Henderson
For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Define hardware exception typesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Disable gateway page emulation for system modeRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Define the rest of the PSWRichard Henderson
We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-05 13:52:15 +0000