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AgeCommit message (Expand)Author
2019-03-20i386: Disable OSPKE on CPU model definitionsEduardo Habkost
2019-03-20i386: Make arch_capabilities migratableEduardo Habkost
2019-03-20i386: kvm: Disable arch_capabilities if MSR can't be setEduardo Habkost
2019-03-19target/riscv: Remove unused structAlistair Francis
2019-03-19RISC-V: Update load reservation comment in do_interruptMichael Clark
2019-03-19RISC-V: Convert trap debugging to trace eventsMichael Clark
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark
2019-03-19RISC-V: Change local interrupts from edge to levelMichael Clark
2019-03-19RISC-V: linux-user support for RVE ABIKito Cheng
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark
2019-03-19riscv: pmp: Log pmp access errors as guest errorsAlistair Francis
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson
2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson
2019-03-19RISC-V: Fixes to CSR_* register macros.Jim Wilson
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann
2019-03-15target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson
2019-03-15target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif
2019-03-15target/arm: change arch timer registers access permissionDongjiu Geng
2019-03-13Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...Peter Maydell
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann
2019-03-12target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle
2019-03-12target/hppa: add TLB protection id checkSven Schnelle