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2023-07-09Merge tag 'pull-tcg-20230709' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
crypto: Provide aes-round.h and host accel # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSqvGodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+1bgf9EG57jfnCQLCfMQ6C # 0bQ0MaeAkGg+7+mUwyi3OPB1VO0yjEKv5pWEnolzrGud35P0KsyoO+msqGqxnbMv # IbhPkQZbmfMsGFPG1DbswjiwmQU5cV+ciONDM+C+qepnuUN+JrzIDHoEFzQRFoQo # eQL/LnuyUkYBvR7YCKNJxFHtwILKcYQPH4jiC6a92C11AzYjDfilSxnuQ2RwL3Tn # Zwf8TKJP5QGExvUdtm8f6xJ1LT7WAvsk9ZTwudE/+XRTnw8RWk6RmZSEQPx+cBdI # p3opaoxkkMrdmcaXbr+9eSfBGq2gsVkKYPiyTDuwVW26575Nob9ZmodT3oSBNlkC # +njd4w== # =Nf5i # -----END PGP SIGNATURE----- # gpg: Signature made Sun 09 Jul 2023 02:55:54 PM BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20230709' of https://gitlab.com/rth7680/qemu: (37 commits) crypto: Unexport AES_*_rot, AES_TeN, AES_TdN crypto: Remove AES_imc crypto: Implement aesdec_IMC with AES_imc_rot crypto: Remove AES_shifts, AES_ishifts target/riscv: Use aesdec_ISB_ISR_IMC_AK target/riscv: Use aesenc_SB_SR_MC_AK target/riscv: Use aesdec_IMC target/riscv: Use aesdec_ISB_ISR_AK target/riscv: Use aesenc_SB_SR_AK target/arm: Use aesdec_IMC target/arm: Use aesenc_MC target/arm: Use aesdec_ISB_ISR_AK target/arm: Use aesenc_SB_SR_AK target/arm: Demultiplex AESE and AESMC target/i386: Use aesdec_ISB_ISR_IMC_AK target/i386: Use aesenc_SB_SR_MC_AK target/i386: Use aesdec_IMC target/i386: Use aesdec_ISB_ISR_AK target/i386: Use aesenc_SB_SR_AK target/ppc: Use aesdec_ISB_ISR_AK_IMC ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/riscv: Use aesdec_ISB_ISR_IMC_AKRichard Henderson
This implements the AES64DSM instruction. This was the last use of aes64_operation and its support macros, so remove them all. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/riscv: Use aesenc_SB_SR_MC_AKRichard Henderson
This implements the AES64ESM instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/riscv: Use aesdec_IMCRichard Henderson
This implements the AES64IM instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/riscv: Use aesdec_ISB_ISR_AKRichard Henderson
This implements the AES64DS instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/riscv: Use aesenc_SB_SR_AKRichard Henderson
This implements the AES64ES instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/arm: Use aesdec_IMCRichard Henderson
This implements the AESIMC instruction. We have converted everything to crypto/aes-round.h; crypto/aes.h is no longer needed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/arm: Use aesenc_MCRichard Henderson
This implements the AESMC instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/arm: Use aesdec_ISB_ISR_AKRichard Henderson
This implements the AESD instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-09target/arm: Use aesenc_SB_SR_AKRichard Henderson
This implements the AESE instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/arm: Demultiplex AESE and AESMCRichard Henderson
Split these helpers so that we are not passing 'decrypt' within the simd descriptor. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/i386: Use aesdec_ISB_ISR_IMC_AKRichard Henderson
This implements the AESDEC instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/i386: Use aesenc_SB_SR_MC_AKRichard Henderson
This implements the AESENC instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/i386: Use aesdec_IMCRichard Henderson
This implements the AESIMC instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/i386: Use aesdec_ISB_ISR_AKRichard Henderson
This implements the AESDECLAST instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/i386: Use aesenc_SB_SR_AKRichard Henderson
This implements the AESENCLAST instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/ppc: Use aesdec_ISB_ISR_AK_IMCRichard Henderson
This implements the VNCIPHER instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/ppc: Use aesenc_SB_SR_MC_AKRichard Henderson
This implements the VCIPHER instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/ppc: Use aesdec_ISB_ISR_AKRichard Henderson
This implements the VNCIPHERLAST instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/ppc: Use aesenc_SB_SR_AKRichard Henderson
This implements the VCIPHERLAST instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/arm: Move aesmc and aesimc tables to crypto/aes.cRichard Henderson
We do not currently have a table in crypto/ for just MixColumns. Move both tables for consistency. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08Merge tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu into ↵Richard Henderson
staging qemu trivial patches for 2023-07-08 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmSo5UsPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZIygH/0z5heVC4CnU5sNuv8GRbXZL7sOXxvoOQf9K # dEBD0/Lzu8QL7mJBpqPuzK4FN/CNnY2nUaGGn3k7U44MrsU6g2P5ksD4Y0hUebkZ # sw+bsaqDeG0J+kZ9IN4V1iLoyGGQ53GDynisZMWY8w/hDmCkoRe5Xy2LZrXS7fgw # LVT04wlxTYG/EwXqMukBYd/S/lap8pUnzgc+VngHmX5gBF4O7qIAZV1j5WobIW6S # /OOOOBZ4YJU9Ha18H4DWrE5+ptfE2sfWAO0z+c/v3bpNTUb9bCyNIE3R3mUwg7z6 # i/96za3R9XH0ChoBWrKHtFn5wygUMGHt63JwIph0bwr73ENVlrE= # =4nBR # -----END PGP SIGNATURE----- # gpg: Signature made Sat 08 Jul 2023 05:25:47 AM BST # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [undefined] # gpg: aka "Michael Tokarev <mjt@debian.org>" [undefined] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu: hw/arm/virt-acpi-build.c: Add missing header migration: unexport migrate_fd_error() migration: factor out "resume_requested" in qmp_migrate() qemu-options.hx: Fix indentation of some option descriptions vdpa: Sort vdpa_feature_bits array alphabetically vdpa: Delete duplicated VIRTIO_NET_F_RSS in vdpa_feature_bits hw: Simplify calls to pci_nic_init_nofail() trivial: man page: document display::gtk::zoom-to-fit target/avr: Fix handling of interrupts above 33. hw/riscv/virt.c: fix typo in 'aia' description Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08target/avr: Fix handling of interrupts above 33.Lucas Dietrich
This commit addresses a bug in the AVR interrupt handling code. The modification involves replacing the usage of the ctz32 function with ctz64 to ensure proper handling of interrupts above 33 in the AVR target. Previously, timers 3, 4, and 5 interrupts were not functioning correctly because most of their interrupt vectors are numbered above 33. Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> (Mjt: updated subject line to have subsytem prefix)
2023-07-07Merge tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson
ppc patch queue for 2023-07-07: In this last queue for 8.1 we have a lot of fixes and improvements all around: SMT support for powerNV, XIVE fixes, PPC440 cleanups, exception handling cleanups and kvm_pph.h cleanups just to name a few. Thanks everyone in the qemu-ppc community for all the contributions for the next QEMU 8.1 release. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZKgihBYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFksr0A/jrvSDSDxB5mR7bo0dNGndLXcdTo # ZGr6k6pcMpr7RDOAAQDVeaw7f8djQ4Aaelk6v1wPs5bYfNY2ElF4NsqHJFX2Cg== # =8lDs # -----END PGP SIGNATURE----- # gpg: Signature made Fri 07 Jul 2023 03:34:44 PM BST # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu: (59 commits) ppc/pnv: Add QME region for P10 target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h' target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h target/ppc: Move CPU QOM definitions to cpu-qom.h target/ppc: Reorder #ifdef'ry in kvm_ppc.h target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h' target/ppc: Machine check on invalid real address access on POWER9/10 tests/qtest: Add xscom tests for powernv10 machine ppc/pnv: Set P10 core xscom region size to match hardware ppc/pnv: Log all unimp warnings with similar message ppc440_pcix: Rename QOM type define abd move it to common header ppc4xx_pci: Add define for ppc4xx-host-bridge type name ppc4xx_pci: Rename QOM type name define ppc440_pcix: Stop using system io region for PCI bus ppc440_pcix: Don't use iomem for regs ppc/sam460ex: Remove address_space_mem local variable ppc440: Remove ppc460ex_pcie_init legacy init function ppc440: Add busnum property to PCIe controller model ppc440: Stop using system io region for PCIe buses ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-07target/i386: Add new CPU model GraniteRapidsTao Su
The GraniteRapids CPU model mainly adds the following new features based on SapphireRapids: - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14] - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21] And adds the following security fix for corresponding vulnerabilities: - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5] - SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13] - FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14] - PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15] - PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24] Signed-off-by: Tao Su <tao1.su@linux.intel.com> Tested-by: Xuelian Guo <xuelian.guo@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20230706054949.66556-7-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-07target/i386: Add few security fix bits in ARCH_CAPABILITIES into ↵Lei Wang
SapphireRapids CPU model SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security fixes. Add version 2 of SapphireRapids CPU model with those bits enabled also. Signed-off-by: Lei Wang <lei4.wang@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Message-ID: <20230706054949.66556-6-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-07target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIESTao Su
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are disclosed for fixing security issues, so add those bit definitions. Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-ID: <20230706054949.66556-5-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-07target/i386: Allow MCDT_NO if host supportsTao Su
MCDT_NO bit indicates HW contains the security fix and doesn't need to be mitigated to avoid data-dependent behaviour for certain instructions. It needs no hypervisor support. Treat it as supported regardless of what KVM reports. Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20230706054949.66556-4-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-07target/i386: Add support for MCDT_NO in CPUID enumerationTao Su
CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior and do not need to be mitigated to avoid data-dependent behavior for certain instructions. Since MCDT_NO is in a new sub-leaf, add a new CPUID feature word FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX. Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20230706054949.66556-3-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-07target/i386: Adjust feature level according to FEAT_7_1_EDXTao Su
If FEAT_7_1_EAX is 0 and FEAT_7_1_EDX is non-zero, as is the case with a Granite Rapids host and '-cpu host,-avx-vnni,-avx512-bf16,-fzrm,-fsrs,-fsrc,-amx-fp16', we can't get CPUID_7_1 leaf even though CPUID_7_1_EDX has non-zero value. Update cpuid_level_func7 according to CPUID_7_1_EDX, otherwise guest may report wrong maximum number sub-leaves in leaf 07H. Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration") Cc: qemu-stable@nongnu.org Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20230706054949.66556-2-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-07target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-ID: <20230627115124.19632-7-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.cPhilippe Mathieu-Daudé
User emulation shouldn't need any of the KVM prototypes declared in "kvm_ppc.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-ID: <20230627115124.19632-6-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.hPhilippe Mathieu-Daudé
TYPE_HOST_POWERPC_CPU is used in various places of cpu_init.c, in order to restrict "kvm_ppc.h" to sysemu, move this QOM-related definition to cpu-qom.h. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-ID: <20230627115124.19632-5-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Move CPU QOM definitions to cpu-qom.hPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230627115124.19632-4-philmd@linaro.org> [dhb: keep cpu_list define in target/ppc/cpu.h] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Reorder #ifdef'ry in kvm_ppc.hPhilippe Mathieu-Daudé
Keep a single if/else/endif block checking CONFIG_KVM. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230627115124.19632-3-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'Philippe Mathieu-Daudé
"kvm_ppc.h" declares: int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run); 'struct kvm_run' is declared in "sysemu/kvm.h", include it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230627115124.19632-2-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Machine check on invalid real address access on POWER9/10Nicholas Piggin
ppc currently silently accepts invalid real address access. Catch these and turn them into machine checks on POWER9/10 machines. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230703120301.45313-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: SMT support for the HID SPRNicholas Piggin
HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Add LPAR-per-core vs per-thread mode flagNicholas Piggin
The Power ISA has the concept of sub-processors: Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that appear to privileged programs as multi-threaded processors with fewer threads. POWER9 and POWER10 have two modes, either every thread is a sub-processor or all threads appear as one multi-threaded processor. In the user manuals these are known as "LPAR per thread" / "Thread LPAR", and "LPAR per core" / "1 LPAR", respectively. The practical difference is: in thread LPAR mode, non-hypervisor SPRs are not shared between threads and msgsndp can not be used to message siblings. In 1 LPAR mode, some SPRs are shared and msgsndp is usable. Thrad LPAR allows multiple partitions to run concurrently on the same core, and is a requirement for KVM to run on POWER9/10 (which does not gang-schedule an LPAR on all threads of a core like POWER8 KVM). Traditionally, SMT in PAPR environments including PowerVM and the pseries QEMU machine with KVM acceleration behaves as in 1 LPAR mode. In OPAL systems, Thread LPAR is used. When adding SMT to the powernv machine, it is therefore preferable to emulate Thread LPAR. To account for this difference between pseries and powernv, an LPAR mode flag is added such that SPRs can be implemented as per-LPAR shared, and that becomes either per-thread or per-core depending on the flag. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target: ppc: Use MSR_HVB bit to get the target endianness for memory dumpNarayana Murty N
Currently on PPC64 qemu always dumps the guest memory in Big Endian (BE) format even though the guest running in Little Endian (LE) mode. So crash tool fails to load the dump as illustrated below: Log : $ virsh dump DOMAIN --memory-only dump.file Domain 'DOMAIN' dumped to dump.file $ crash vmlinux dump.file <snip> crash 8.0.2-1.el9 WARNING: endian mismatch: crash utility: little-endian dump.file: big-endian WARNING: machine type mismatch: crash utility: PPC64 dump.file: (unknown) crash: dump.file: not a supported file format <snip> This happens because cpu_get_dump_info() passes cpu->env->has_hv_mode to function ppc_interrupts_little_endian(), the cpu->env->has_hv_mode always set for powerNV even though the guest is not running in hv mode. The hv mode should be taken from msr_mask MSR_HVB bit (cpu->env.msr_mask & MSR_HVB). This patch fixes the issue by passing MSR_HVB value to ppc_interrupts_little_endian() in order to determine the guest endianness. The crash tool also expects guest kernel endianness should match the endianness of the dump. The patch was tested on POWER9 box booted with Linux as host in following cases: Host-Endianess Qemu-Target-Machine Qemu-Generated-Guest Memory-Dump-Format BE powernv(OPAL/PowerNV) LE BE powernv(OPAL/PowerNV) BE LE powernv(OPAL/PowerNV) LE LE powernv(OPAL/PowerNV) BE LE pseries(OPAL/PowerNV/pSeries) KVMHV LE LE pseries TCG LE Fixes: 5609400a4228 ("target/ppc: Set the correct endianness for powernv memory dumps") Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Vaibhav Jain <vaibhav@linux.ibm.com> Message-ID: <20230623072506.34713-1-nnmlinux@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Get CPUState in one stepBALATON Zoltan
We can get CPUState from env with env_cpu without going through PowerPCCPU and casting that. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <28424220f37f51ce97f24cadc7538a9c0d16cb45.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppd: Remove unused defineBALATON Zoltan
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop the unused define as well. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <50adc24f9d408882128e896d8a81a1a059c41836.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Remove some more local CPUState variables only used onceBALATON Zoltan
Some helpers only have a CPUState local to call cpu_interrupt_exittb() but we can use env_cpu for that and remove the local. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <aa34e449552c6ab52d48938ccbe762fc06adac01.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Move common check in exception handlers to a functionBALATON Zoltan
All powerpc exception handlers share some code when handling machine check exceptions. Move this to a common function. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <9cfffaa35aa894086dd092af6b0b26f2d62ff3de.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Remove unneeded parameter from powerpc_reset_wakeup()BALATON Zoltan
CPUState is rarely needed by this function (only for logging a fatal error) and it's easy to get from the env parameter so passing it separately is not necessary. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <f42761401c708fd6e02f7523d9f709b1972e5863.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Remove some superfluous parenthesesBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <8384ed0f7335093012bbd3d28fb2a543a2e7346c.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Fix icount access for some hypervisor instructionsNicholas Piggin
Several instructions and register access require icount reads and are missing translator_io_start(). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230625103700.8992-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Add TFMR SPR implementation with read and write helpersNicholas Piggin
TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). Add helpers for the TFMR register, which will form part of the core timebase facility model in future but for now behaviour is unchanged. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230625120317.13877-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Tidy POWER book4 SPR registrationNicholas Piggin
POWER book4 (implementation-specific) SPRs are sometimes in their own functions, but in other cases are mixed with architected SPRs. Do some spring cleaning on these. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230625120317.13877-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Only generate decodetree files when TCG is enabledPhilippe Mathieu-Daudé
No need to generate TCG-specific decodetree files when TCG is disabled. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230626140100.67941-1-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-26 06:28:49 +0000