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AgeCommit message (Expand)Author
2023-01-12target/arm: Fix sve_probe_pageRichard Henderson
2023-01-11target/i386: fix operand size of unary SSE operationsPaolo Bonzini
2023-01-11target/i386: Remove compilation errors when -Werror=maybe-uninitializedEric Auger
2023-01-11i386: Emit correct error code for 64-bit IDT entryJoe Richey
2023-01-09Merge tag 'pull-request-2023-01-09' of https://gitlab.com/thuth/qemu into sta...Peter Maydell
2023-01-09target/s390x: Restrict sysemu/reset.h to system emulationPhilippe Mathieu-Daudé
2023-01-09target/s390x/tcg/excp_helper: Restrict system headers to sysemuPhilippe Mathieu-Daudé
2023-01-09target/s390x/tcg/misc_helper: Remove unused "memory.h" includePhilippe Mathieu-Daudé
2023-01-09hw/s390x/pv: Restrict Protected Virtualization to sysemuPhilippe Mathieu-Daudé
2023-01-08Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell
2023-01-06Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
2023-01-06Merge tag 'pull-hex-20230105' of https://github.com/quic/qemu into stagingPeter Maydell
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng
2023-01-06target/riscv: Simplify helper_sret() a little bitBin Meng
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson
2023-01-06target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2023-01-06target/riscv: generate virtual instruction exceptionMayuresh Chitale
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei
2023-01-06target/i386: Add SGX aex-notify and EDECCSSA supportKai Huang
2023-01-06KVM: remove support for kernel-irqchip=offPaolo Bonzini
2023-01-05target/sparc: Avoid TCGV_{LOW,HIGH}Richard Henderson
2023-01-05Hexagon (target/hexagon) implement mutability mask for GPRsMarco Liebel
2023-01-05target/hexagon: suppress unused variable warningAlessandro Di Federico
2023-01-05target/hexagon/idef-parser: fix two typos in READMEMatheus Tavares Bernardino
2023-01-05target/hexagon: rename aliased register HEX_REG_P3_0Mukilan Thiyagarajan
2023-01-05target/arm: align exposed ID registers with LinuxZhuojia Shen
2023-01-05target/arm: cleanup cpu includesClaudio Fontana
2023-01-05target/arm: Remove unused includes from helper.cFabiano Rosas
2023-01-05target/arm: Remove unused includes from m_helper.cFabiano Rosas
2023-01-05target/arm: Fix checkpatch brace errors in helper.cFabiano Rosas
2023-01-05target/arm: Fix checkpatch space errors in helper.cFabiano Rosas
2023-01-05target/arm: Fix checkpatch comment style warnings in helper.cFabiano Rosas
2023-01-05target/arm: fix handling of HLT semihosting in system modeAlex Bennée
2023-01-05target/arm: Add ARM Cortex-R52 CPUTobias Röhmel
2023-01-05target/arm: Add PMSAv8r functionalityTobias Röhmel
2023-01-05target/arm: Add PMSAv8r registersTobias Röhmel
2023-01-05target/arm: Enable TTBCR_EAE for ARMv8-R AArch32Tobias Röhmel
2023-01-05target/arm: Make stage_2_format for cache attributes optionalTobias Röhmel
2023-01-05target/arm: Make RVBAR available for all ARMv8 CPUsTobias Röhmel