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2017-09-08ppc64: introduce e6500KONRAD Frederic
2017-09-08booke206: allow to specify an mmucfg value at the initKONRAD Frederic
2017-09-08booke206: fix tlbnps for fixed size TLBKONRAD Frederic
2017-09-08booke206: fix booke206_tlbnps for mav 2.0KONRAD Frederic
2017-09-08ppc: spapr: Make VCPU ID handling private to SPAPRSam Bobroff
2017-09-08ppc: spapr: Rename cpu_dt_id to vcpu_idSam Bobroff
2017-09-07Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...Peter Maydell
2017-09-07target/arm: Add Jazelle featurePortia Stephens
2017-09-07target/arm: Implement new do_transaction_failed hookPeter Maydell
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell
2017-09-07target/arm: Move regime_is_secure() to target/arm/internals.hPeter Maydell
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8MPeter Maydell
2017-09-07target/arm: Make VTOR register banked for v8MPeter Maydell
2017-09-07target/arm: Make CONTROL register banked for v8MPeter Maydell
2017-09-07target/arm: Make FAULTMASK register banked for v8MPeter Maydell
2017-09-07target/arm: Make PRIMASK register banked for v8MPeter Maydell
2017-09-07target/arm: Make BASEPRI register banked for v8MPeter Maydell
2017-09-07target/arm: Add MMU indexes for secure v8MPeter Maydell
2017-09-07target/arm: Register second AddressSpace for secure v8M CPUsPeter Maydell
2017-09-07target/arm: Add state field, feature bit and migration for v8M secure statePeter Maydell
2017-09-07target/arm: Implement new PMSAv8 behaviourPeter Maydell
2017-09-07target/arm: Implement ARMv8M's PMSAv8 registersPeter Maydell
2017-09-06target/arm: Perform per-insn cross-page check only for ThumbRichard Henderson
2017-09-06target/arm: Split out thumb_tr_translate_insnRichard Henderson
2017-09-06target/arm: Move ss check to init_disas_contextRichard Henderson
2017-09-06target/arm: [a64] Move page and ss checks to init_disas_contextRichard Henderson
2017-09-06target/arm: [tcg] Port to generic translation frameworkLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to disas_logLluís Vilanova
2017-09-06target/arm: [tcg] Port to disas_logLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to tb_stopLluís Vilanova
2017-09-06target/arm: [tcg] Port to tb_stopLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to translate_insnLluís Vilanova
2017-09-06target/arm: [tcg] Port to translate_insnLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to breakpoint_checkLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to insn_startLluís Vilanova
2017-09-06target/arm: [tcg] Port to insn_startLluís Vilanova
2017-09-06target/arm: [tcg] Port to tb_startLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to init_disas_contextLluís Vilanova
2017-09-06target/arm: [tcg] Port to init_disas_contextLluís Vilanova
2017-09-06target/arm: [tcg] Port to DisasContextBaseLluís Vilanova
2017-09-06target/i386: [tcg] Port to generic translation frameworkLluís Vilanova
2017-09-06target/i386: [tcg] Port to disas_logLluís Vilanova
2017-09-06target/i386: [tcg] Port to tb_stopLluís Vilanova
2017-09-06target/i386: [tcg] Port to translate_insnLluís Vilanova