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AgeCommit message (Expand)Author
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
2018-01-24Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into stagingPeter Maydell
2018-01-22target/xtensa: disas/xtensa: fix coverity warningsMax Filippov
2018-01-22target/xtensa: add sample_controller coreMax Filippov
2018-01-22target/xtensa: allow different default CPU for MMU/noMMUMax Filippov
2018-01-12target/xtensa: Remove duplicate typedef of DisasContextPeter Maydell
2018-01-11target/xtensa: add de212 coreMax Filippov
2018-01-11target/xtensa: fix default sysrom/sysram addressesMax Filippov
2018-01-09target/xtensa: implement disassemblerMax Filippov
2018-01-09target/xtensa: implement const16Max Filippov
2018-01-09target/xtensa: implement GPIO32Max Filippov
2018-01-09target/xtensa: implement salt/saltuMax Filippov
2018-01-09target/xtensa: add internal/noop SRs and opcodesMax Filippov
2018-01-09target/xtensa: drop DisasContext::litbaseMax Filippov
2018-01-09target/xtensa: use libisa for instruction decodingMax Filippov
2017-12-18target/xtensa: switch fsf to libisaMax Filippov
2017-12-18target/xtensa: switch dc233c to libisaMax Filippov
2017-12-18target/xtensa: switch dc232b to libisaMax Filippov
2017-12-18target/xtensa: update import_core.sh script for libisaMax Filippov
2017-12-18target/xtensa: extract FPU2000 opcode translatorsMax Filippov
2017-12-18target/xtensa: extract core opcode translatorsMax Filippov
2017-12-18target/xtensa: import libisa sourceMax Filippov
2017-12-18target/xtensa: pass actual frame size to the entry helperMax Filippov
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2017-10-27xtensa: cleanup cpu type name compositionIgor Mammedov
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
2017-10-25disas: Remove unused flags argumentsRichard Henderson
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé
2017-09-26target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macroAlistair Francis
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
2017-09-01xtensa: replace cpu_xtensa_init() with cpu_generic_init()Igor Mammedov
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-07-14char: add backend hotswap handlerAnton Nefedov
2017-07-11target/xtensa: gdbstub: drop dead return statementMax Filippov
2017-06-06target/xtensa: handle unknown registers in gdbstubMax Filippov
2017-06-06target/xtensa: support output to chardev consoleMax Filippov
2017-06-06target/xtensa: fix return value of read/write simcallsMax Filippov
2017-06-06target/xtensa: fix mapping direction in read/write simcallsMax Filippov
2017-03-18Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into stagingPeter Maydell
2017-03-11target/xtensa: fix semihosting argc/argv implementationMax Filippov
2017-03-09target/xtensa: hold BQL for interrupt processingAlex Bennée
2017-02-23target/xtensa: add two missing headers to core import scriptMax Filippov
2017-02-23target/xtensa: sim: instantiate local memoriesMax Filippov
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth
2017-01-25Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov