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2018-08-06target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfnThomas Huth
The instance_init function of the xtensa CPUs creates a memory region, but does not set an owner, so the memory region is not destroyed correctly when the CPU object is removed. This can happen when introspecting the CPU devices, so introspecting the CPU device will leave a dangling memory region object in the QOM tree. Make sure to set the right owner here to fix this issue. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 1532005320-17794-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02hw/xtensa: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé
It eases code review, unit is explicit. Patch generated using: $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/ $ git grep -n '[<>][<>]= ?[1-5]0' and modified manually. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20180625124238.25339-22-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-30xtensa: Avoid calling get_page_addr_code() from helper functionPeter Maydell
The xtensa frontend calls get_page_addr_code() from its itlb_hit_test helper function. This function is really part of the TCG core's internals, and calling it from a target helper makes it awkward to make changes to that core code. It also means that we don't pass the correct retaddr to tlb_fill(), so we won't correctly handle the case where an exception is generated. The helper is used for the instructions IHI, IHU and IPFL. Change it to call cpu_ldb_code_ra() instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-30target/xtensa: Convert to TranslatorOpsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Change gen_intermediate_code dc to pointerRichard Henderson
This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Convert to DisasContextBaseRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURNRichard Henderson
The usage of DISAS_UPDATE is after noreturn helpers. It is thus indistinguishable from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: check zero overhead loop alignmentMax Filippov
ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-28move public invalidate APIs out of translate-all.{c,h}, clean upPaolo Bonzini
Place them in exec.c, exec-all.h and ram_addr.h. This removes knowledge of translate-all.h (which is an internal header) from several files outside accel/tcg and removes knowledge of AddressSpace from translate-all.c (as it only operates on ram_addr_t). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-08target/xtensa: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 20180606152128.449-12-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-04Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into ↵Peter Maydell
staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tcg-next-pull-request: tcg: Pass tb and index to tcg_gen_exit_tb separately Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-01Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Linux header upgrade (Peter) * firmware.json definition (Laszlo) * IPMI migration fix (Corey) * QOM improvements (Alexey, Philippe, me) * Memory API cleanups (Jay, me, Tristan, Peter) * WHPX fixes and improvements (Lucian) * Chardev fixes (Marc-André) * IOMMU documentation improvements (Peter) * Coverity fixes (Peter, Philippe) * Include cleanup (Philippe) * -clock deprecation (Thomas) * Disable -sandbox unless CONFIG_SECCOMP (Yi Min Zhao) * Configurability improvements (me) # gpg: Signature made Fri 01 Jun 2018 17:42:13 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (56 commits) hw: make virtio devices configurable via default-configs/ hw: allow compiling out SCSI memory: Make operations using MemoryRegionIoeventfd struct pass by pointer. char: Remove unwanted crlf conversion qdev: Remove DeviceClass::init() and ::exit() qdev: Simplify the SysBusDeviceClass::init path hw/i2c: Use DeviceClass::realize instead of I2CSlaveClass::init hw/i2c/smbus: Use DeviceClass::realize instead of SMBusDeviceClass::init target/i386/kvm.c: Remove compatibility shim for KVM_HINTS_REALTIME Update Linux headers to 4.17-rc6 target/i386/kvm.c: Handle renaming of KVM_HINTS_DEDICATED scripts/update-linux-headers: Handle kernel license no longer being one file scripts/update-linux-headers: Handle __aligned_u64 virtio-gpu-3d: Define VIRTIO_GPU_CAPSET_VIRGL2 elsewhere gdbstub: Prevent fd leakage docs/interop: add "firmware.json" ipmi: Use proper struct reference for KCS vmstate vmstate: Add a VSTRUCT type tcg: remove softfloat from --disable-tcg builds qemu-options: Mark the non-functional -clock option as deprecated ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé
Code change produced with: $ git grep '#include "exec/exec-all.h"' | \ cut -d: -f-1 | \ xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \ xargs sed -i.bak '/#include "exec\/exec-all.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-10-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target/xtensa: Include "qemu/timer.h" to use NANOSECONDS_PER_SECONDPhilippe Mathieu-Daudé
Since d0ce7e9cfc the dc232b structure uses the NANOSECONDS_PER_SECOND definition from "qemu/timer.h". Include it to allow further includes cleanup. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-7-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31Make tb_invalidate_phys_addr() take a MemTxAttrs argumentPeter Maydell
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to tb_invalidate_phys_addr(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
2018-05-21Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into ↵Peter Maydell
staging trivial patches for 2018-05-20 # gpg: Signature made Sun 20 May 2018 07:13:20 BST # gpg: using RSA key 701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * remotes/mjt/tags/trivial-patches-fetch: (22 commits) acpi: fix a comment about aml_call0() qapi/net.json: Fix the version number of the "vlan" removal gdbstub: Handle errors in gdb_accept() gdbstub: Use qemu_set_cloexec() replace functions which are only available in glib-2.24 typedefs: Remove PcGuestInfo from qemu/typedefs.h qemu-options: Allow -no-user-config again hw/timer/mt48t59: Fix bit-rotten NVRAM_PRINTF format strings Remove unnecessary variables for function return value trivial: Do not include pci.h if it is not necessary tests: fix tpm-crb tpm-tis tests race hw/ide/ahci: Keep ALLWINNER_AHCI() macro internal qemu-img-cmds.hx: add passive-aggressive note qemu-img: Make documentation between .texi and .hx consistent qemu-img: remove references to GEN_DOCS qemu-img.texi: fix command ordering qemu-img-commands.hx: argument ordering fixups HACKING: document preference for g_new instead of g_malloc qemu-option-trace: -trace enable= is a pattern, not a file slirp/debug: Print IP addresses in human readable form ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-20Remove unnecessary variables for function return valueLaurent Vivier
Re-run Coccinelle script scripts/coccinelle/return_directly.cocci Signed-off-by: Laurent Vivier <lvivier@redhat.com> ppc part Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2018-05-18target/xtensa: Honor CPU_DUMP_FPURichard Henderson
Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension # gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/riscv/translate.c
2018-05-10target/xtensa: Use new min/max expandersRichard Henderson
The generic expanders replace nearly identical code in the translator. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-09target/xtensa: avoid integer overflow in next_page PC checkEmilio G. Cota
If the PC is in the last page of the address space, next_page_start overflows to 0. Fix it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-04-11icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk
In icount mode, instructions that access io memory spaces in the middle of the translation block invoke TB recompilation. After recompilation, such instructions become last in the TB and are allowed to access io memory spaces. When the code includes instruction like i386 'xchg eax, 0xffffd080' which accesses APIC, QEMU goes into an infinite loop of the recompilation. This instruction includes two memory accesses - one read and one write. After the first access, APIC calls cpu_report_tpr_access, which restores the CPU state to get the current eip. But cpu_restore_state_from_tb resets the cpu->can_do_io flag which makes the second memory access invalid. Therefore the second memory access causes a recompilation of the block. Then these operations repeat again and again. This patch moves resetting cpu->can_do_io flag from cpu_restore_state_from_tb to cpu_loop_exit* functions. It also adds a parameter for cpu_restore_state which controls restoring icount. There is no need to restore icount when we only query CPU state without breaking the TB. Restoring it in such cases leads to the incorrect flow of the virtual time. In most cases new parameter is true (icount should be recalculated). But there are two cases in i386 and openrisc when the CPU state is only queried without the need to break the TB. This patch fixes both of these cases. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Message-Id: <20180409091320.12504.35329.stgit@pasha-VirtualBox> [rth: Make can_do_io setting unconditional; move from cpu_exec; make cpu_loop_exit_{noexc,restore} call cpu_loop_exit.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-26target/xtensa: fix timers testMax Filippov
The value of CCOUNT special register is calculated as time elapsed since CCOUNT == 0 multiplied by the core frequency. In icount mode time increment between consecutive instructions that don't involve time warps is constant, but unless the result of multiplication of this constant by the core frequency is a whole number the CCOUNT increment between these instructions may not be constant. E.g. with icount=7 each instruction takes 128ns, with core clock of 10MHz CCOUNT values for consecutive instructions are: 502: (128 * 502 * 10000000) / 1000000000 = 642.56 503: (128 * 503 * 10000000) / 1000000000 = 643.84 504: (128 * 504 * 10000000) / 1000000000 = 645.12 I.e.the CCOUNT increments depend on the absolute time. This results in varying CCOUNT differences for consecutive instructions in tests that involve time warps and don't set CCOUNT explicitly. Change frequency of the core used in tests so that clock cycle takes exactly 64ns. Change icount power used in tests to 6, so that each instruction takes exactly 1 clock cycle. With these changes CCOUNT increments only depend on the number of executed instructions and that's what timer tests expect, so they work correctly. Longer story: http://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg04326.html Cc: Pavel Dovgaluk <Pavel.Dovgaluk@ispras.ru> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-26target/xtensa/import_core.sh: fix #include <xtensa-isa.h>Max Filippov
Change #include <xtensa-isa.h> to #include "xtensa-isa.h" in imported files to make references to local files consistent. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-26target/xtensa: add .inc. to non-top level source file namesMax Filippov
Fix definitions of existing cores and core importing script to follow the rule of naming non-top level source files. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov
it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-16target/xtensa: add linux-user supportMax Filippov
Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-13target/xtensa: support MTTCGMax Filippov
- emit TCG barriers for MEMW, EXTW, S32RI and L32AI; - do atomic_cmpxchg_i32 for S32C1I. Cc: Emilio G. Cota <cota@braap.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-13target/xtensa: use correct number of registers in gdbstubMax Filippov
System emulation should provide access to all registers, userspace emulation should only provide access to unprivileged registers. Record register flags from GDB register map definition, calculate both num_regs and num_core_regs if either is zero. Use num_regs in system emulation, num_core_regs in userspace emulation gdbstub. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-13target/xtensa: mark register windows in the dumpMax Filippov
Add arrows that mark beginning of register windows and position of the current window in the windowed register file. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-13target/xtensa: dump correct physical registersMax Filippov
xtensa_cpu_dump_state outputs CPU physical registers as is, without synchronization from current window. That may result in different values printed for the current window and corresponding physical registers. Synchronize physical registers from window before dumping. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-09Clean up includesMarkus Armbruster
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes, with the change to target/s390x/gen-features.c manually reverted, and blank lines around deletions collapsed. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-3-armbru@redhat.com>
2018-02-09Use #include "..." for our own headers, <...> for othersMarkus Armbruster
System headers should be included with <...>, our own headers with "...". Offenders tracked down with an ugly, brittle and probably buggy Perl script. Previous iteration was commit a9c94277f0. Delete inclusions of "string.h" and "strings.h" instead of fixing them to <string.h> and <strings.h>, because we always include these via osdep.h. Put the cleaned up system header includes first. While there, separate #include from file comment with exactly one blank line. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-2-armbru@redhat.com>
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
2018-01-24Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into stagingPeter Maydell
target/xtensa updates: - make mini-bootloader independent of the initial CPU state; - add noMMU XTFPGA variants; - add two noMMU cores: de212 and sample_controller; - fix issues reported by coverity against xtensa translator and disassembler. # gpg: Signature made Mon 22 Jan 2018 20:00:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180122-xtensa: target/xtensa: disas/xtensa: fix coverity warnings target/xtensa: add sample_controller core target/xtensa: allow different default CPU for MMU/noMMU target/xtensa: add de212 core hw/xtensa/xtfpga: support noMMU cores hw/xtensa/xtfpga: extract flash configuration hw/xtensa: extract xtensa_create_memory_regions target/xtensa: fix default sysrom/sysram addresses hw/xtensa/xtfpga: clean up function/structure names hw/xtensa/xtfpga: rewrite mini bootloader Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-22target/xtensa: disas/xtensa: fix coverity warningsMax Filippov
Coverity warnings CID 1385146, 1385148 1385149 and 1385150 point that xtensa_opcode_num_operands and xtensa_format_num_slots may return -1 even when xtensa_opcode_decode and xtensa_format_decode succeed. In that case unsigned counters used to iterate through operands/slots will not do the right thing. Make counters and loop bounds signed to fix the warnings. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-22target/xtensa: add sample_controller coreMax Filippov
The sample_controller core is a simple noMMU general purpose core, modern analog of de212. It is used as a default core in the xtensa port of Zephyr. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-22target/xtensa: allow different default CPU for MMU/noMMUMax Filippov
Define default core for noMMU configurations and use that core as machine default with noMMU XTFPGA machines. This is done to avoid offering non-working configuration (MMU core on a noMMU machine) as a default. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-12target/xtensa: Remove duplicate typedef of DisasContextPeter Maydell
Some older versions of gcc complain if a typedef is defined twice: target/xtensa/translate.c:81: error: redefinition of typedef 'DisasContext' target/xtensa/cpu.h:339: note: previous declaration of 'DisasContext' was here Remove the now-redundant typedef from the definition of the struct in translate.c. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1515762528-22818-1-git-send-email-peter.maydell@linaro.org
2018-01-11target/xtensa: add de212 coreMax Filippov
DE212 is a noMMU core supported in linux. Import this core to provide true noMMU configuration for xtensa linux to run on QEMU. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-11target/xtensa: fix default sysrom/sysram addressesMax Filippov
noMMU configs had wrong sysrom and sysram base addresses, fix them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement disassemblerMax Filippov
Add disas/xtensa.c and use libisa for instruction decoding/opcode name lookup. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement const16Max Filippov
const16 is an opcode that shifts 16 lower bits of an address register to the 16 upper bits and puts its immediate operand into the lower 16 bits. It is not controlled by an Xtensa option and doesn't have a fixed opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement GPIO32Max Filippov
GPIO32 is not in the core ISA, but it was widely used in Diamond Cores. This implementation doesn't do actual I/O and doesn't handle the case of GPIO32 state being a part of coprocessor. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: implement salt/saltuMax Filippov
SALT/SALTU are recent additions to the core Xtensa ISA that do signed/unsigned setcond. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: add internal/noop SRs and opcodesMax Filippov
Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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