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2019-02-18target/xtensa: allow multiple names for single opcodeMax Filippov
There are opcodes that differ only in encoding or possible range of immediate arguments. Allow multiple names for single opcode translation table entry to reduce code duplication in that case. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: don't require opcode table sortingMax Filippov
Requirement for alphabetical opcode sorting in opcode tables is awkward and does not allow sharing implementation between multiple opcodes. Use hash tables to find opcodes by name. Move implementation from the translate.c to the helper.c to its only user and remove declaration from the cpu.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov
Don't run xtensa_finalize_config at the time of core registration, instead run it at the CPU class initialization. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: fixup test_mmuhifi_c3 overlayMax Filippov
xtensa-modules part of the test_mmuhifi_c3 core is missing fixes that returns XTENSA_UNDEFINED for undefined opcodes and marks all data structures static. Run sed script from target/xtensa/import_core.sh on it. This fixes test_sr tests for missing special registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-11target/xtensa: get rid of gen_callw[i]Max Filippov
Merge gen_callwi and gen_callw into their only users, translate_callw and translate_callxw. Extract jump slot adjustment logic into a separate function and use it in gen_jumpi and translate_callw. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-10target/xtensa: don't specify windowed registers manuallyMax Filippov
Use libisa to extract whether opcode uses windowed registers and construct mask based on that. This only leaves special case for the 'entry' opcode, as it needs to probe a register dynamically. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-08target/xtensa/import_core.sh: don't add duplicate 'static'Max Filippov
xtensa-modules.c produced by recent Tensilica tools have Opcode_*_encode_fns arrays defined as static. Don't add extra 'static' in front of them when importing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-28target/xtensa: add test_mmuhifi_c3 coreMax Filippov
test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-28target/xtensa: expose core runstall as an IRQ lineMax Filippov
Runstall signal looks very much like a level-triggered IRQ line. Provide xtensa_get_runstall function that returns runstall IRQ. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-28target/xtensa: rearrange access to external interruptsMax Filippov
Replace xtensa_get_extint that returns single external IRQ descriptor with xtensa_get_extints that returns a vector of all external IRQs. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-28target/xtensa: drop function xtensa_timer_irqMax Filippov
It's a one-liner used in a single place, move its implementation there and remove its declaration. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24target/xtensa: fix access to the INTERRUPT SRMax Filippov
INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24target/xtensa: add qemu_cpu_kick to xtensa_runstallMax Filippov
When xtensa_runstall is called to unstall a core it needs to kick it after clearing runstall flag, otherwise the core doesn't start immediately. There's also no point in clearing CPU_INTERRUPT_HALT, drop it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: move non-HELPER functions to helper.cMax Filippov
Move remaining non-HELPER functions from op_helper.c to helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: drop dump_state helperMax Filippov
Drop unused helper dump_state from op_helper.c Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: extract interrupt and exception helpersMax Filippov
Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: extract debug helpersMax Filippov
Move HELPER functions related to native debugging from op_helper.c to dbg_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: extract MMU helpersMax Filippov
Move MMU-related helper functions from op_helper.c and helper.c to mmu_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: extract windowed registers helpersMax Filippov
Move helper functions related to register windows from op_helper.c to win_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-13target/xtensa: extract FPU helpersMax Filippov
Move FPU-related HELPER functions from op_helper.c to fpu_helper.c No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-11target/xtensa: rework zero overhead loops implementationMax Filippov
Don't invalidate TB with the end of zero overhead loop when LBEG or LEND change. Instead encode the distance from the start of the page where the TB starts to the LEND in the TB cs_base and generate loopback code when the next PC matches encoded LEND. Distance to a destination within the same page and up to a maximum instruction length into the next page is encoded literally, otherwise it's zero. The distance from LEND to LBEG is also encoded in the cs_base: it's encoded literally when less than 256 or as 0 otherwise. This allows for TB chaining for the loopback branch at the end of a loop for the most common loop sizes. With this change the resulting emulation speed is about 10% higher in softmmu mode on uClibc-ng and LTP tests. Emulation speed in linux user mode is a few percent lower because there's no direct TB chaining between different memory pages. Testing with lower limit on direct TB chaining range shows gradual slowdown to ~15% for the block size of 64 bytes and ~50% for the block size of 32 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-11-20target/xtensa: drop num_[core_]regs from dc232b/dc233c configsMax Filippov
Now that xtensa_count_regs does the right thing, remove manual initialization of these fields from the affected configurations and let xtensa_finalize_config initialize them. Add XTREG_END to terminate register lists. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-11-20target/xtensa: gdbstub fix register countingMax Filippov
In order to communicate correctly with gdb xtensa gdbstub must provide expected number of registers in 'g' packet response. xtensa-elf-gdb expects both nonprivileged and privileged registers. xtensa-linux-gdb only expects nonprivileged registers. gdb only counts one contiguous stretch of registers, do the same for the core registers in the xtensa_count_regs. With this change qemu-system-xtensa is able to communicate with all xtensa-elf-gdb versions (versions prior to 8.2 require overlay fixup), and qemu-xtensa is able to communicate with all xtensa-linux-gdb versions, except 8.2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract gen_check_interrupts callMax Filippov
- mark instructions that affect active IRQ level; - put call for gen_check_interrupts right after the instruction translation; when FLIX is enabled it will need to appear before other exits from the TB as well; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: make rsr/wsr helpers return voidMax Filippov
Now that all logic for TB termination is extracted from rsr/wsr their return value is not used and may be dropped. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract unconditional TB termination via slot 0Max Filippov
- mark instructions that require TB termination via slot 0; - put TB termination right after the instruction translation loop, if termination w/o TB linking wasn't requested; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: always end TB on CCOUNT access/CCOMPARE writeMax Filippov
Currently we only end TB in icount mode, because access to CCOUNT or write to CCOMPARE are IO operations. Simplify the behaviour a bit and end TB unconditionally. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: change SR number checks to assertionsMax Filippov
Opcode decoding with libisa takes care about range of valid group SRs, like CCOMPARE, IBREAKA, DBREAKA or DBREAKC. Turn range checks in wsr implementations into assertions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract unconditional TB terminationMax Filippov
- mark all instructions that exit TB and require dynamic search for the next TB; - put TB termination right after the instruction translation loop; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for division by zeroMax Filippov
- mark quos/quou/rems/remu instructions; - drop parameter 0 from the translate_quou and split translate_remu from it; - put test for division by zero exception right after the coprocessor exception test; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for cpdisabled exceptionMax Filippov
- add XtensaOpcodeOps::coprocessor with bitmask of coprocessors used by the instruction; - replace coprocessor id parameter of gen_check_cpenable with the bitmask of used coprocessors; - collect coprocessor IDs used by an instruction in the disassembly loop; - put test for coprocessor disabled exception after the alloca test; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for alloca exceptionMax Filippov
- mark movsp instruction; - put test for alloca exception right after the test for window underflow; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for window underflow exceptionMax Filippov
- mark retw and retw.n instructions; - extract window inderflow test from retw helper; - put underflow exception check generation right after the overflow check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for window overflow exceptionMax Filippov
- add ps.callinc to the TB flags, that allows testing all instructions for window overflow statically; - drop gen_window_check* functions; replace them with get_window_check that accepts bitmask of used registers; - add XtensaOpcodeOps::test_overflow that returns bitmask of implicitly used registers; use it for entry and call{,x}{4,8,12}; - drop window overflow test from the entry helper; - drop parameter 0 from translate_[di]cache and use translate_nop for d/i cache opcodes that don't need memory accessibility check; - add bitmask XtensaOpcodeOps::windowed_register_op that marks opcode arguments that refer to windowed registers; - translate windowed_register_op mask to a mask of actually used registers in the disassembly loop; - add check for window overflow right after the check for debug exception; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for debug exceptionMax Filippov
- mark break and break.n instructions; - collect debug cause bits from parameter 0 of instructions marked for debug exception; - put debug exception check right after syscall check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for syscall instructionMax Filippov
- mark syscall instruction; - put syscall exception check right after privileged exception check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for privileged instructionMax Filippov
- mark privileged instructions; - put single privileged instruction check after disassembly loop; - translate_[di]cache: drop parameter 0, shift parameters one down; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for an illegal instructionMax Filippov
- TB flags: add XTENSA_TBFLAG_CWOE that corresponds to the architectural CWOE state; - entry: move CWOE check from the helper to the test_ill_entry; - retw: move CWOE check from the helper to the test_ill_retw; - separate instruction disassembly loop and translation loop; save disassembly results in local array; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: support input from chardev consoleMax Filippov
Complete xtensa-semi chardev console implementation: allow reading input characters from file descriptor 0 and call sys_select_one simcall on it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov
s32c1i must load and store value with target endianness, not host. This results in an infinite loop in atomic cmpxchg sequences when target endianness doesn't match host endianness. Fixes: 9fb40342d4b3 ("target/xtensa: support MTTCG") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-09-17target/xtensa: fix FPU2000 bugsMax Filippov
- FPU2000 defines rfr and wfr opcodes, not rfr.s and wfr.s; - movcond.s uses incorrect operand in tcg_gen_movcond: in case the condition is not satisfied it must not change its argument 0. Fixes: c04e1692e3aa ("target/xtensa: extract FPU2000 opcode translators") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: convert to do_transaction_failedMax Filippov
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-19target/xtensa: add test_kc705_be coreMax Filippov
This is big-endian core with HiFi2 instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-19target/xtensa: clean up gdbstub register handlingMax Filippov
- move register counting to xtensa/gdbstub.c - add symbolic names for register types and flags from GDB and use them in register counting and access functions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-19target/xtensa: fix gdbstub register countsMax Filippov
This fixes communication with gdb in the presence of type-5 (TIE state mapped on user registers) and type-7 (special case of masked registers) registers in the xtensa core config. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-06target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfnThomas Huth
The instance_init function of the xtensa CPUs creates a memory region, but does not set an owner, so the memory region is not destroyed correctly when the CPU object is removed. This can happen when introspecting the CPU devices, so introspecting the CPU device will leave a dangling memory region object in the QOM tree. Make sure to set the right owner here to fix this issue. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 1532005320-17794-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02hw/xtensa: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé
It eases code review, unit is explicit. Patch generated using: $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/ $ git grep -n '[<>][<>]= ?[1-5]0' and modified manually. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20180625124238.25339-22-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-30xtensa: Avoid calling get_page_addr_code() from helper functionPeter Maydell
The xtensa frontend calls get_page_addr_code() from its itlb_hit_test helper function. This function is really part of the TCG core's internals, and calling it from a target helper makes it awkward to make changes to that core code. It also means that we don't pass the correct retaddr to tlb_fill(), so we won't correctly handle the case where an exception is generated. The helper is used for the instructions IHI, IHU and IPFL. Change it to call cpu_ldb_code_ra() instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-30target/xtensa: Convert to TranslatorOpsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Change gen_intermediate_code dc to pointerRichard Henderson
This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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